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https://github.com/aap/pdp6.git
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329 lines
6.4 KiB
Verilog
329 lines
6.4 KiB
Verilog
module tto(input wire clk,
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input wire tto_clock,
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input wire [8:1] iob,
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input wire tty_data_clr,
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input wire tty_data_set,
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output wire tx,
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output reg tto_done = 0
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);
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reg [8:1] tto;
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reg tto_out_line;
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reg tto_enable = 0;
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reg tto_active = 0;
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reg tto_active0;
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reg tto_div2 = 0;
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reg tto_div20;
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wire tto_4count;
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wire tto_shift = tto_div20 & ~tto_div2;
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count4 c(.clk(clk),
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.reset(tto_active0 & ~tto_active),
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.enable(tto_clock),
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.out(tto_4count));
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always @(posedge clk) begin
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tto_active0 <= tto_active;
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tto_div20 <= tto_div2;
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if(tty_data_clr) begin
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tto_done <= 0;
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end
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if(tty_data_set) begin
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tto <= iob;
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tto_enable <= 1;
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end
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if(tto_clock) begin
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if(tto_active)
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tto_div2 <= ~tto_div2;
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if(tto_4count & tto_enable)
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tto_active <= 1;
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end
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if(tto_shift) begin
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tto_enable <= 0;
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{ tto, tto_out_line } <= { tto_enable, tto };
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if(~tto_enable & tto[8:2] == 0) begin
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tto_active <= 0;
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tto_done <= 1;
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end
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end
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if(~tto_active)
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tto_out_line <= 1;
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else
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if(~tto_active0)
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tto_out_line <= 0;
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end
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assign tx = tto_out_line;
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endmodule
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module tti(input wire clk,
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input wire tti_clock,
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input wire rx,
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output wire [8:1] iob,
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output reg tti_active = 0,
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output reg tti_done = 0,
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output reg [8:1] tti = 0
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);
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assign iob = tti;
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wire tti_shift = tti_4count_rise & ~tti_last_unit;
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reg tti_last_unit = 0;
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reg tti_active0;
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wire tti_4count;
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reg tti_4count0;
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wire tti_space = ~rx;
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wire tti_4count_rise = ~tti_4count0 & tti_4count;
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wire tti_set = ~tti_active0 & tti_active;
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div8 d(.clk(clk),
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.reset(tti_set),
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.enable(tti_clock & tti_active),
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.out(tti_4count));
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always @(posedge clk) begin
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tti_4count0 <= tti_4count;
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tti_active0 <= tti_active;
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if(tti_set) begin
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tti <= 8'o377;
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tti_last_unit <= 0;
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end
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if(tti_4count_rise & tti_last_unit)
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tti_active <= 0;
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if(tti_shift) begin
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tti <= { rx, tti[8:2] };
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if(~tti[1]) begin
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tti_last_unit <= 1;
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tti_done <= 1;
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end
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if(tti[1])
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tti_done <= 0;
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if(~tti_space & (& tti))
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tti_active <= 0;
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end
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if(tti_clock)
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if(~tti_active & tti_space)
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tti_active <= 1;
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end
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endmodule
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module tty(
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input wire clk,
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input wire rx,
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output wire tx,
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output wire [7:0] tti_ind,
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output wire [6:0] status_ind,
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input wire iobus_iob_poweron,
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input wire iobus_iob_reset,
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input wire iobus_datao_clear,
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input wire iobus_datao_set,
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input wire iobus_cono_clear,
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input wire iobus_cono_set,
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input wire iobus_iob_fm_datai,
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input wire iobus_iob_fm_status,
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input wire [3:9] iobus_ios,
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input wire [0:35] iobus_iob_in,
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output wire [1:7] iobus_pi_req,
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output wire [0:35] iobus_iob_out
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);
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wire clk2;
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clk14khz clock2(.inclk(clk),
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.outclk(clk2));
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wire tti_clock, tto_clock;
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clk16div ttidiv(.clk(clk),
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.inclk(clk2),
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.outclk(tti_clock));
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clk4div ttodiv(.clk(clk),
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.inclk(tti_clock),
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.outclk(tto_clock));
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wire tty_sel = iobus_ios == 7'b001_010_0;
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wire tty_data_clr;
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wire tty_data_set;
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wire tty_ic_clr;
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wire tty_ic_set;
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wire tty_reset;
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wire tty_datai = tty_sel & iobus_iob_fm_datai;
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wire tty_status = tty_sel & iobus_iob_fm_status;
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pg tty_pg0(.clk(clk), .reset(0),
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.in(tty_sel & iobus_datao_clear),
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.p(tty_data_clr));
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pg tty_pg1(.clk(clk), .reset(0),
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.in(tty_sel & iobus_datao_set),
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.p(tty_data_set));
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pg tty_pg2(.clk(clk), .reset(0),
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.in(tty_sel & iobus_cono_clear),
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.p(tty_ic_clr));
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pg tty_pg3(.clk(clk), .reset(0),
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.in(tty_sel & iobus_cono_set),
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.p(tty_ic_set));
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pg tty_pg4(.clk(clk), .reset(0),
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.in(iobus_iob_reset),
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.p(tty_reset));
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assign iobus_iob_out =
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tty_datai ? { 28'b0, tti_ind } :
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tty_status ? { 29'b0, tti_busy, tti_flag, tto_busy, tto_flag, tty_pia } :
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36'b0;
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wire [0:7] tty_req = { tti_flag | tto_flag, 7'b0 } >> tty_pia;
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assign iobus_pi_req = tty_req[1:7];
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reg [33:35] tty_pia = 0;
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reg tti_busy = 0;
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reg tti_flag = 0;
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reg tto_busy = 0;
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reg tto_flag = 0;
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wire tto_done;
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reg tto_done0;
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wire tti_done;
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reg tti_done0;
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wire tti_active;
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reg tti_active0;
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assign status_ind = { tti_busy, tti_flag, tto_busy, tto_flag, tty_pia };
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always @(posedge clk) begin
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tti_done0 <= tti_done;
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tto_done0 <= tto_done;
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tti_active0 <= tti_active;
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if(tty_ic_clr | tty_reset)
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tty_pia <= 0;
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if(tty_reset) begin
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tto_busy <= 0;
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tto_flag <= 0;
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tti_busy <= 0;
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tti_flag <= 0;
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end
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if(tty_ic_set) begin
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tty_pia <= iobus_iob_in[33:35];
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if(iobus_iob_in[25])
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tti_busy <= 0;
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if(iobus_iob_in[26])
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tti_flag <= 0;
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if(iobus_iob_in[27])
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tto_busy <= 0;
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if(iobus_iob_in[28])
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tto_flag <= 0;
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if(iobus_iob_in[29])
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tti_busy <= 1;
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if(iobus_iob_in[30])
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tti_flag <= 1;
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if(iobus_iob_in[31])
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tto_busy <= 1;
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if(iobus_iob_in[32])
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tto_flag <= 1;
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end
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if(tty_data_clr) begin
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tto_flag <= 0;
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tto_busy <= 1;
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end
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if(~tto_done0 & tto_done) begin
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tto_flag <= 1;
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tto_busy <= 0;
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end
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if(tty_datai)
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tti_flag <= 0;
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if(~tti_active0 & tti_active)
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tti_busy <= 1;
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if(~tti_done0 & tti_done) begin
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tti_flag <= 1;
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tti_busy <= 0;
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end
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end
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wire [8:1] iob;
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tti tti0(.clk(clk),
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.tti_clock(tti_clock),
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.rx(rx),
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.iob(iob),
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.tti_active(tti_active),
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.tti_done(tti_done),
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.tti(tti_ind));
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tto tto0(.clk(clk),
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.tto_clock(tto_clock),
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.iob(iobus_iob_in[28:35]),
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.tty_data_clr(tty_data_clr),
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.tty_data_set(tty_data_set),
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.tx(tx),
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.tto_done(tto_done));
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endmodule
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module clk14khz(input wire inclk,
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output wire outclk);
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reg [11:0] cnt = 0;
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assign outclk = cnt == 3551;
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always @(posedge inclk)
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if(outclk)
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cnt <= 0;
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else
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cnt <= cnt + 12'b1;
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endmodule
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module clk16div(input wire clk,
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input wire inclk,
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output wire outclk
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);
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reg [4:0] cnt = 0;
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assign outclk = cnt == 16;
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always @(posedge clk)
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if(outclk)
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cnt <= 0;
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else if(inclk)
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cnt <= cnt + 5'b1;
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endmodule
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module div8(
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input wire clk,
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input wire reset,
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input wire enable,
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output wire out
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);
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reg [2:0] cnt = 4;
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always @(posedge clk)
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if(reset)
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cnt <= 0;
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else if(enable)
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cnt <= cnt + 3'b1;
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assign out = cnt[2];
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endmodule
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module count4(
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input wire clk,
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input wire reset,
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input wire enable,
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output wire out
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);
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reg [1:0] cnt = 0;
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always @(posedge clk)
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if(reset)
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cnt <= 0;
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else if(enable && cnt != 3)
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cnt <= cnt + 2'b1;
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assign out = cnt == 3;
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endmodule
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module clk4div(input wire clk,
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input wire inclk,
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output wire outclk
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);
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reg [2:0] cnt = 0;
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assign outclk = cnt == 4;
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always @(posedge clk)
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if(outclk)
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cnt <= 0;
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else if(inclk)
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cnt <= cnt + 3'b1;
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endmodule
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