aap f41c186d88 memory files

2016-04-15 01:19:00 +02:00

apr.c

wrote some basic test and found bugs

2016-04-14 23:42:19 +02:00

extra_panel.png

key cycle and memory control basically working

2015-10-30 19:41:54 +01:00

ind_panel.png

key cycle and memory control basically working

2015-10-30 19:41:54 +01:00

io.c

worked on execution cycle

2015-11-07 19:51:36 +01:00

key_d.png

key cycle and memory control basically working

2015-10-30 19:41:54 +01:00

key_n.png

key cycle and memory control basically working

2015-10-30 19:41:54 +01:00

key_u.png

key cycle and memory control basically working

2015-10-30 19:41:54 +01:00

lamp_off.png

key cycle and memory control basically working

2015-10-30 19:41:54 +01:00

lamp_on.png

key cycle and memory control basically working

2015-10-30 19:41:54 +01:00

LICENSE

Initial commit

2015-10-30 19:40:17 +01:00

main.c

memory files

2016-04-15 01:19:00 +02:00

Makefile

better pulse system; revisited key cycle

2016-04-05 00:50:38 +02:00

mem

memory files

2016-04-15 01:19:00 +02:00

mem.c

memory files

2016-04-15 01:19:00 +02:00

op_panel.png

key cycle and memory control basically working

2015-10-30 19:41:54 +01:00

pdp6.h

memory files

2016-04-15 01:19:00 +02:00

switch_d.png

key cycle and memory control basically working

2015-10-30 19:41:54 +01:00

switch_u.png

key cycle and memory control basically working

2015-10-30 19:41:54 +01:00

Description

PDP-6 Emulator and Verilog Simulation

MIT 3.1 MiB

Languages

C 79%

PHP 9.1%

Pawn 6.8%

Pascal 3.7%

Assembly 0.6%

Other 0.8%