github.com/antonblanchard.chiselwatt
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Add mcrf

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2020-03-02 22:11:27 +11:00
committed by Anton Blanchard
parent 6f6141249b
commit 06563749f9
4 changed files with 12 additions and 3 deletions
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6
scripts/instructions.yaml
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@@ -1768,6 +1768,12 @@ mtocrf:
compare: CMP_RC_0
fxm: FXM_ONEHOT
mcrf:
unit: U_CR
internalOp: CR_MCRF
rOut: ROUT_NONE
compare: CMP_RC_0
b:
unit: U_BR
internalOp: BR_UNCOND

5
src/main/scala/Control.scala
View File

@@ -37,8 +37,9 @@ object Control {
val SPR_MF = 0.U(2.W)
val SPR_MT = 1.U(2.W)
val CR_MF = 0.U(2.W)
val CR_MT = 1.U(2.W)
val CR_MF = 0.U(2.W)
val CR_MT = 1.U(2.W)
val CR_MCRF = 2.U(2.W)
val BR_UNCOND = 0.U(2.W)
val BR_COND = 1.U(2.W)

2
src/main/scala/Core.scala
View File

@@ -240,6 +240,8 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
conditionRegister := fxm.asBools.zip(conditionRegister).zip(executeRs(31, 0).nibbles().reverse).map({ case ((fxm, cr), reg) =>
Mux(fxm, reg, cr)
})
} .elsewhen (ctrl.internalOp === CR_MCRF) {
conditionRegister(insn_bf(executeInsn)) := conditionRegister(insn_bfa(executeInsn))
}
}

2
src/main/scala/Instructions.scala
View File

@@ -164,6 +164,7 @@ object Instructions {
def MFOCRF = BitPat("b011111?????1?????????0000010011?")
def MTCRF = BitPat("b011111?????0?????????0010010000?")
def MTOCRF = BitPat("b011111?????1?????????0010010000?")
def MCRF = BitPat("b010011???????????????0000000000?")
// SPR read/write
def MFSPR = BitPat("b011111???????????????0101010011?")
@@ -214,7 +215,6 @@ object Instructions {
//def DCBZ = BitPat("b011111???????????????1111110110?")
//def MCRF = BitPat("b010011???????????????0000000000?")
//def ISEL = BitPat("b011111????????????????????01111?") // 2.03
//def PRTYD = BitPat("b011111???????????????0010111010?") // 2.05