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Make clock frequency settable at the top level of Core

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Rather than hardwiring LoadStore.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Michael Neuling
2021-02-22 16:33:04 +11:00
committed by Joel Stanley
parent 2c44cd8bce
commit 21cdff7976
2 changed files with 8 additions and 8 deletions
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6
src/main/scala/Core.scala
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@@ -6,7 +6,7 @@ import Control._
import Helpers._ import Helpers._
import InstructionHelpers._ import InstructionHelpers._
class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends Module { class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int, clockFreq: Int) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val tx = Output(UInt(1.W)) val tx = Output(UInt(1.W))
val rx = Input(UInt(1.W)) val rx = Input(UInt(1.W))
@@ -40,7 +40,7 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
val multiplier = Module(new SimpleMultiplier(bits)) val multiplier = Module(new SimpleMultiplier(bits))
val divider = Module(new SimpleDivider(bits)) val divider = Module(new SimpleDivider(bits))
val mem = Module(new MemoryBlackBoxWrapper(bits, memWords, memFileName)) val mem = Module(new MemoryBlackBoxWrapper(bits, memWords, memFileName))
val loadStore = Module(new LoadStore(bits, memWords)) val loadStore = Module(new LoadStore(bits, memWords, clockFreq))
val control = Module(new Control(bits)) val control = Module(new Control(bits))
val regFile = Module(new RegisterFile(32, bits, 3, 1, false)) val regFile = Module(new RegisterFile(32, bits, 3, 1, false))
@@ -445,5 +445,5 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
} }
object CoreObj extends App { object CoreObj extends App {
(new ChiselStage).emitVerilog(new Core(64, 384*1024, "insns.hex", 0x0)) (new ChiselStage).emitVerilog(new Core(64, 384*1024, "insns.hex", 0x0, 50000000))
} }

10
src/main/scala/LoadStore.scala
View File

@@ -32,7 +32,7 @@ class LoadStoreInput(val bits: Int) extends Bundle {
* 2C: form store mask, store data * 2C: form store mask, store data
*/ */
class LoadStore(val bits: Int, val words: Int) extends Module { class LoadStore(val bits: Int, val words: Int, val clockFreq: Int) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val in = Flipped(Valid(new LoadStoreInput(bits))) val in = Flipped(Valid(new LoadStoreInput(bits)))
val out = Output(Valid(UInt(bits.W))) val out = Output(Valid(UInt(bits.W)))
@@ -166,7 +166,7 @@ class LoadStore(val bits: Int, val words: Int) extends Module {
} }
when (addr(7, 0) === "h20".U) { when (addr(7, 0) === "h20".U) {
/* SYS_REG_CLKINFO */ /* SYS_REG_CLKINFO */
data := 50000000.U data := clockFreq.asUInt(bits.W)
} }
} }
@@ -203,13 +203,13 @@ class LoadStore(val bits: Int, val words: Int) extends Module {
} }
} }
class LoadStoreWrapper(val bits: Int, val size: Int, filename: String) extends Module { class LoadStoreWrapper(val bits: Int, val size: Int, val clockFreq: Int, filename: String) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val in = Flipped(Valid(new LoadStoreInput(bits))) val in = Flipped(Valid(new LoadStoreInput(bits)))
val out = Output(Valid(UInt(bits.W))) val out = Output(Valid(UInt(bits.W)))
}) })
val loadStore = Module(new LoadStore(bits, size/(bits/8))) val loadStore = Module(new LoadStore(bits, size/(bits/8), clockFreq))
val mem = Module(new MemoryBlackBoxWrapper(bits, size/(bits/8), filename)) val mem = Module(new MemoryBlackBoxWrapper(bits, size/(bits/8), filename))
io.in <> loadStore.io.in io.in <> loadStore.io.in
@@ -226,5 +226,5 @@ class LoadStoreWrapper(val bits: Int, val size: Int, filename: String) extends M
} }
object LoadStoreObj extends App { object LoadStoreObj extends App {
(new ChiselStage).emitVerilog(new LoadStoreWrapper(64, 128*1024, "test.hex")) (new ChiselStage).emitVerilog(new LoadStoreWrapper(64, 128*1024, 50000000, "test.hex"))
} }