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Add syscon regsiters to the loadstore unit

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This adds a really simple syscon so the potato uart in micropython can
operate.

Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Joel Stanley 2021-02-22 13:52:01 +10:30
parent 23824ad377
commit 2c44cd8bce
1 changed files with 20 additions and 0 deletions
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20
src/main/scala/LoadStore.scala
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@ -150,6 +150,26 @@ class LoadStore(val bits: Int, val words: Int) extends Module {
data := d.zeroExtend(length)
}
/* Syscon */
when (addr(31, 8) === "hc00000".U) {
when (addr(7, 0) === "h00".U) {
/* SYS_REG_SIGNATURE */
data := "hf00daa5500010001".U
}
when (addr(7, 0) === "h08".U) {
/*
* SYS_REG_INFO
* SYS_REG_INFO_HAS_UART is true
* Other bits are false
*/
data := "h1".U
}
when (addr(7, 0) === "h20".U) {
/* SYS_REG_CLKINFO */
data := 50000000.U
}
}
/* UART */
when (addr(31, 8) === "hc00020".U) {
when (addr(7, 0) === "h08".U) {