Add Radiona ULX3S ECP5-85F Board

Signed-off-by: Carlos de Paula <me@carlosedp.com>

Makefile

@@ -36,6 +36,14 @@ PACKAGE=CABGA381
 NEXTPNR_FLAGS=--um5g-85k --freq 12
 OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
+else ifeq ($(ECP5_BOARD),ulx3s)
+# Radiona ULX3S with ECP5-85F
+LPF=constraints/ecp5-ulx3s.lpf
+PLL=pll/pll_ehxplll_25MHz.v
+PACKAGE=CABGA381
+NEXTPNR_FLAGS=--85k --freq 25
+OPENOCD_JTAG_CONFIG=openocd/ft231x.cfg
+OPENOCD_DEVICE_CONFIG=openocd/LFE5U-85F.cfg
 else ifeq ($(ECP5_BOARD),orangecrab)
 # OrangeCrab with ECP85
 LPF=constraints/orange-crab.lpf
@@ -85,7 +93,7 @@ dockerlator: chiselwatt
 synth: test-vars chiselwatt.bit
 
 test-vars:
-	@test -n "$(LPF)" || (echo "If synthesizing, use \"synth\" target with ECP5_BOARD variable to either \"evn\", \"orangecrab\", \"colorlight\"\n" ; exit 1)
+	@test -n "$(LPF)" || (echo "If synthesizing, use \"synth\" target with ECP5_BOARD variable to either \"evn\", \"ulx3s\", \"orangecrab\", \"colorlight\"\n" ; exit 1)
 
 chiselwatt.json: insns.hex $(verilog_files) $(PLL) toplevel.v
 	$(YOSYS) -p "read_verilog -sv $(verilog_files) $(PLL) toplevel.v; synth_ecp5 -json $@ -top toplevel"

README.md

@@ -94,6 +94,7 @@ ln -s hello_world/hello_world.hex insns.hex
 The `Makefile` currently supports the following FPGA boards by defining the `ECP5_BOARD` parameter on make:
 
 * Lattice [ECP5 Evaluation Board](http://www.latticesemi.com/ecp5-evaluation) - `evn`
+* Radiona [ULX3S](https://radiona.org/ulx3s/) - `ulx3s`
 * Greg Davill [Orangecrab](https://github.com/gregdavill/OrangeCrab) - `orangecrab`
 * Q3k [Colorlight](https://github.com/q3k/chubby75/tree/master/5a-75b) - `colorlight`
 
@@ -134,16 +135,16 @@ Then link in the micropython image:
 ln -s micropython/firmware.hex insns.hex
 ```
 
-For example, to build for the Orangecrab, run:
+For example, to build for the ULX3S, run:
 
 ```sh
-make ECP5_BOARD=orangecrab synth`
+make ECP5_BOARD=ulx3s synth`
 ```
 
 and to program the FPGA:
 
 ```sh
-make ECP5_BOARD=orangecrab prog
+make ECP5_BOARD=ulx3s prog
 ```
 
 ## Simple Python script for reading USB serial port

constraints/ecp5-ulx3s.lpf

@@ -0,0 +1,20 @@
+LOCATE COMP "clock" SITE "G2";
+IOBUF PORT "clock" PULLMODE=NONE IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clock" 25 MHZ;
+
+LOCATE COMP "reset" SITE "D7";
+IOBUF PORT "reset" PULLMODE=UP IO_TYPE=LVCMOS33;
+
+LOCATE COMP "io_tx" SITE "M1";
+LOCATE COMP "io_rx" SITE "L4";
+
+IOBUF PORT "io_tx" IO_TYPE=LVCMOS33;
+IOBUF PORT "io_rx" IO_TYPE=LVCMOS33;
+
+LOCATE COMP "io_terminate" SITE "B2";
+LOCATE COMP "io_ledB" SITE "C2";
+LOCATE COMP "io_ledC" SITE "C1";
+
+IOBUF PORT "io_terminate" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "io_ledB" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "io_ledC" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;

openocd/ecp5-ulx3s.cfg

@@ -0,0 +1,19 @@
+# this supports Radiona ULX3S EXP5 Board
+
+# file: ecp5.ocd
+telnet_port 4444
+gdb_port 3333
+
+# JTAG TAPs
+jtag newtap lfe5 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5
+
+# -expected-id should match ECP5 CHIP_ID:
+# 12F: 0x21111043
+# 25F: 0x41111043
+# 45F: 0x41112043
+# 85F: 0x41113043
+
+init
+scan_chain
+svf -tap lfe5.tap -quiet -progress chiselwatt.svf
+shutdown

openocd/ft231x.cfg

@@ -0,0 +1,14 @@
+# this supports Radiona ULX3s ECP5 Board
+
+# file: ft231x.ocd
+interface ft232r
+ft232r_vid_pid 0x0403 0x6015
+# ft232r_serial_desc 123456
+ft232r_tck_num DSR
+ft232r_tms_num DCD
+ft232r_tdi_num RI
+ft232r_tdo_num CTS
+ft232r_trst_num RTS
+ft232r_srst_num DTR
+ft232r_restore_serial 0x15
+adapter_khz 1000