1
0
mirror of https://github.com/antonblanchard/chiselwatt.git synced 2026-02-09 01:41:17 +00:00

Fix another reference to Makefile.synth in README.md

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2020-01-30 07:35:23 +11:00
committed by Anton Blanchard
parent 9b13565996
commit 729c02c8c9

View File

@@ -61,7 +61,7 @@ scripts/bin2hex.py ../micropython/ports/powerpc/build/firmware.bin > insns.hex
Synthesis on FPGAs is supported with yosys/nextpnr. It uses Docker images, so no software other
than Docker needs to be installed. If you prefer podman you can use that too.
Edit Makefile.synth to configure your FPGA, JTAG device etc. You will also need to configure the
Edit Makefile to configure your FPGA, JTAG device etc. You will also need to configure the
amount of block RAM your FPGA supports, by editing `src/main/scala/Core.scala`. Here we are using
128kB of block RAM: