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Code Releases Activity

Move some of the CR handling into its own unit

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2020-01-31 21:01:15 +11:00
committed by Anton Blanchard
parent fb166bbfae
commit 737ba98e02
4 changed files with 49 additions and 29 deletions
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4
scripts/instructions.yaml
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@@ -1742,6 +1742,7 @@ mfcr:
unit: U_CR
internalOp: CR_MF
rOut: ROUT_RT
crOut: N
compare: CMP_RC_0
fxm: FXM_FF
@@ -1749,6 +1750,7 @@ mfocrf:
unit: U_CR
internalOp: CR_MF
rOut: ROUT_RT
crOut: N
compare: CMP_RC_0
fxm: FXM_ONEHOT
@@ -1757,6 +1759,7 @@ mtcrf:
internalOp: CR_MT
rS: RS_RS
rOut: ROUT_NONE
crOut: Y
compare: CMP_RC_0
fxm: FXM
@@ -1765,6 +1768,7 @@ mtocrf:
internalOp: CR_MT
rS: RS_RS
rOut: ROUT_NONE
crOut: Y
compare: CMP_RC_0
fxm: FXM_ONEHOT

25
src/main/scala/ConditionRegisterUnit.scala Normal file
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@@ -0,0 +1,25 @@
import chisel3._
import Helpers._
class ConditionRegisterUnit extends Module {
val io = IO(new Bundle {
val fxm = Input(UInt(8.W))
val rs = Input(UInt(32.W))
val conditionRegisterIn = Input(Vec(8, UInt(4.W)))
val conditionRegisterOut = Output(Vec(8, UInt(4.W)))
val gprOut = Output(UInt(32.W))
})
io.gprOut := io.fxm.asBools.zip(io.conditionRegisterIn).map({
case (f, c) => Mux(f, c, 0.U)
}).reduce(_ ## _)
io.conditionRegisterOut := io.fxm.asBools.zip(io.conditionRegisterIn).zip(io.rs.nibbles().reverse).map({
case ((fxm, cr), reg) => Mux(fxm, reg, cr)
})
}
object ConditionRegisterUnitObj extends App {
chisel3.Driver.execute(Array[String](), () => new ConditionRegisterUnit)
}

8
src/main/scala/Control.scala
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@@ -242,10 +242,10 @@ object Control {
CMPLW -> List(U_ADD, DC, RA_RA, RB_RB, DC, ROUT_NONE, CA_1, DC, DC, Y, CMP_CMP, Y, N, Y, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC),
MFSPR -> List(U_SPR, SPR_MF, DC, DC, DC, ROUT_RT, DC, DC, DC, DC, CMP_RC_0, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC),
MTSPR -> List(U_SPR, SPR_MT, DC, DC, RS_RS, ROUT_NONE, DC, DC, DC, DC, CMP_RC_0, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC),
MFCR -> List(U_CR, CR_MF, DC, DC, DC, ROUT_RT, DC, DC, DC, DC, CMP_RC_0, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, FXM_FF, DC),
MFOCRF -> List(U_CR, CR_MF, DC, DC, DC, ROUT_RT, DC, DC, DC, DC, CMP_RC_0, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, FXM_ONEHOT, DC),
MTCRF -> List(U_CR, CR_MT, DC, DC, RS_RS, ROUT_NONE, DC, DC, DC, DC, CMP_RC_0, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, FXM, DC),
MTOCRF -> List(U_CR, CR_MT, DC, DC, RS_RS, ROUT_NONE, DC, DC, DC, DC, CMP_RC_0, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, FXM_ONEHOT, DC),
MFCR -> List(U_CR, CR_MF, DC, DC, DC, ROUT_RT, DC, DC, DC, N, CMP_RC_0, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, FXM_FF, DC),
MFOCRF -> List(U_CR, CR_MF, DC, DC, DC, ROUT_RT, DC, DC, DC, N, CMP_RC_0, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, FXM_ONEHOT, DC),
MTCRF -> List(U_CR, CR_MT, DC, DC, RS_RS, ROUT_NONE, DC, DC, DC, Y, CMP_RC_0, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, FXM, DC),
MTOCRF -> List(U_CR, CR_MT, DC, DC, RS_RS, ROUT_NONE, DC, DC, DC, Y, CMP_RC_0, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, FXM_ONEHOT, DC),
B -> List(U_BR, BR_UNCOND, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, BR_TARGET_NONE),
BC -> List(U_BR, BR_COND, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, BR_TARGET_NONE),
BCLR -> List(U_BR, BR_COND, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, DC, BR_TARGET_LR),

41
src/main/scala/Core.scala
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@@ -28,6 +28,7 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
val mem = Module(new MemoryBlackBoxWrapper(bits, memWords, memFileName))
val loadStore = Module(new LoadStore(bits, memWords))
val control = Module(new Control(bits))
val conditionRegisterUnit = Module(new ConditionRegisterUnit)
val regFile = Module(new RegisterFile(32, bits, 3, 1, false))
val carry = RegInit(0.U(1.W))
@@ -176,6 +177,15 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
loadStore.io.in.valid := true.B
}
val fxm = MuxLookup(ctrl.fxm, "hFF".U, Array(
FXM -> insn_fxm(executeInsn),
FXM_ONEHOT -> { val f = insn_fxm_onehot(executeInsn); Mux(f === 0.U, "h80".U, f) }
))
conditionRegisterUnit.io.fxm := fxm
conditionRegisterUnit.io.rs := executeRs
conditionRegisterUnit.io.conditionRegisterIn := conditionRegister
val xerRegisterNum = 1
val linkRegisterNum = 8
val CountRegisterNum = 9
@@ -205,30 +215,6 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
}
}
val crOut = RegInit(0.U(bits.W))
when (executeValid && (ctrl.unit === U_CR)) {
val fxm = WireDefault(UInt(8.W), 0.U)
when (ctrl.fxm === FXM_FF) {
fxm := "hFF".U
} .elsewhen (ctrl.fxm === FXM) {
fxm := insn_fxm(executeInsn)
} .elsewhen (ctrl.fxm === FXM_ONEHOT) {
val f = insn_fxm_onehot(executeInsn)
fxm := Mux(f === 0.U, "h80".U, f)
}
when (ctrl.internalOp === CR_MF) {
crOut := fxm.asBools.zip(conditionRegister).map({ case (f, c) =>
Mux(f, c, 0.U)
}).reduce(_ ## _)
} .elsewhen (ctrl.internalOp === CR_MT) {
conditionRegister := fxm.asBools.zip(conditionRegister).zip(executeRs(31, 0).nibbles().reverse).map({ case ((fxm, cr), reg) =>
Mux(fxm, reg, cr)
})
}
}
when (executeValid && (ctrl.unit === U_BR)) {
val branchTaken = WireDefault(Bool(), false.B)
@@ -278,6 +264,8 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
val rotatorCarryOut = RegNext(rotator.io.carryOut)
val populationCountOut = RegNext(populationCount.io.out)
val countZeroesOut = RegNext(countZeroes.io.out)
val conditionRegisterGprOut = RegNext(conditionRegisterUnit.io.gprOut)
val conditionRegisterCrOut = RegNext(conditionRegisterUnit.io.conditionRegisterOut)
when (executeValid && (ctrl.unit === U_ILL)) {
illegal := true.B
@@ -315,6 +303,7 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
writebackRc := (ctrl.compare === CMP_RC_1) || ((ctrl.compare === CMP_RC_RC) && insn_rc(executeInsn).asBool)
}
val writebackConditionRegisterWrite = RegNext(executeValid && (ctrl.unit === U_CR) && (ctrl.crOut === true.B))
val writebackCmp = RegNext(ctrl.compare === CMP_CMP)
val writebackCrField = RegNext(insn_bf(executeInsn))
// Compare instructions need to know if a comparison is 32 bit
@@ -328,7 +317,7 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
U_POP -> populationCountOut,
U_ZER -> countZeroesOut,
U_SPR -> sprOut,
U_CR -> crOut,
U_CR -> conditionRegisterGprOut,
U_MUL -> multiplier.io.out.bits,
U_DIV -> divider.io.out.bits,
U_LDST -> loadStore.io.out.bits))
@@ -371,6 +360,8 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
} .elsewhen (writebackFastValid && writebackCmp) {
conditionRegister(writebackCrField) :=
cmp(wrData, adderLtOut, writebackIs32bit)
} .elsewhen (writebackConditionRegisterWrite) {
conditionRegister := conditionRegisterCrOut
}
val completed = RegNext(writebackFastValid || multiplier.io.out.valid || loadStore.io.out.valid || divider.io.out.valid)