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Need reg on pll_bypass.v outputs
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
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Anton Blanchard
parent
c4ac79c1d7
commit
8293ade696
@@ -1,7 +1,7 @@
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module pll(
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input clki,
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output clko,
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output lock
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output reg clko,
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output reg lock
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);
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always @* begin
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