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Use cache inhibited load and store instructions

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2020-04-09 11:59:11 +10:00
committed by Anton Blanchard
parent 4c9d475f5b
commit a1b6ddc329
5 changed files with 153 additions and 56 deletions
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hello_world/hello_world.bin
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hello_world/hello_world.elf
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93
hello_world/hello_world.hex
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@@ -40,7 +40,7 @@ a64b5a7d14004a39
60211f0064210000
618c00003d800000
658c0000798c07c6
7d8903a6618c113c
7d8903a6618c1014
480000004e800421
0000000000000000
0000000000000000
@@ -513,74 +513,55 @@ a64b5a7d14004a39
e8010010ebc1fff0
7c0803a6ebe1fff8
3c4000014e800020
7c0802a63842a000
3fe2fffffbe1fff8
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48000051f821ffd1
7fe3fb7860000000
6000000048000139
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60000000480000e1
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4bffffec60000000
0100000000000000
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3940001a3d20c000
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0000000000000000
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0000000000000000
3c40000100000000
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3842a0003c400001
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108
scripts/instructions.yaml
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@@ -972,6 +972,114 @@ ldbrx:
update: N
reservation: N
lbzcix:
unit: U_LDST
internalOp: LDST_LOAD
rA: RA_RA_OR_ZERO
rB: RB_RB
rOut: ROUT_RT
compare: CMP_RC_0
length: LEN_1B
signed: N
byteReverse: N
update: N
reservation: N
ldcix:
unit: U_LDST
internalOp: LDST_LOAD
rA: RA_RA_OR_ZERO
rB: RB_RB
rOut: ROUT_RT
compare: CMP_RC_0
length: LEN_8B
signed: N
byteReverse: N
update: N
reservation: N
lhzcix:
unit: U_LDST
internalOp: LDST_LOAD
rA: RA_RA_OR_ZERO
rB: RB_RB
rOut: ROUT_RT
compare: CMP_RC_0
length: LEN_2B
signed: N
byteReverse: N
update: N
reservation: N
lwzcix:
unit: U_LDST
internalOp: LDST_LOAD
rA: RA_RA_OR_ZERO
rB: RB_RB
rOut: ROUT_RT
compare: CMP_RC_0
length: LEN_4B
signed: N
byteReverse: N
update: N
reservation: N
stbcix:
unit: U_LDST
internalOp: LDST_STORE
rA: RA_RA_OR_ZERO
rB: RB_RB
rS: RS_RS
rOut: ROUT_NONE
compare: CMP_RC_0
length: LEN_1B
signed: N
byteReverse: N
update: N
reservation: N
stdcix:
unit: U_LDST
internalOp: LDST_STORE
rA: RA_RA_OR_ZERO
rB: RB_RB
rS: RS_RS
rOut: ROUT_NONE
compare: CMP_RC_0
length: LEN_8B
signed: N
byteReverse: N
update: N
reservation: N
sthcix:
unit: U_LDST
internalOp: LDST_STORE
rA: RA_RA_OR_ZERO
rB: RB_RB
rS: RS_RS
rOut: ROUT_NONE
compare: CMP_RC_0
length: LEN_2B
signed: N
byteReverse: N
update: N
reservation: N
stwcix:
unit: U_LDST
internalOp: LDST_STORE
rA: RA_RA_OR_ZERO
rB: RB_RB
rS: RS_RS
rOut: ROUT_NONE
compare: CMP_RC_0
length: LEN_4B
signed: N
byteReverse: N
update: N
reservation: N
ldx:
unit: U_LDST
internalOp: LDST_LOAD

8
src/main/scala/Control.scala
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@@ -174,6 +174,14 @@ object Control {
LWZUX -> List(U_LDST, LDST_LOAD, RA_RA_OR_ZERO, RB_RB, DC, ROUT_RT, CA_0, DC, DC, DC, CMP_RC_0, DC, N, N, DC, DC, DC, DC, LEN_4B, N, Y, N, DC, DC, DC, DC, DC),
LDARX -> List(U_LDST, LDST_LOAD, RA_RA_OR_ZERO, RB_RB, DC, ROUT_RT, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_8B, N, N, Y, DC, DC, DC, DC, DC),
LDBRX -> List(U_LDST, LDST_LOAD, RA_RA_OR_ZERO, RB_RB, DC, ROUT_RT, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_8B, Y, N, N, DC, DC, DC, DC, DC),
LBZCIX -> List(U_LDST, LDST_LOAD, RA_RA_OR_ZERO, RB_RB, DC, ROUT_RT, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_1B, N, N, N, DC, DC, DC, DC, DC),
LDCIX -> List(U_LDST, LDST_LOAD, RA_RA_OR_ZERO, RB_RB, DC, ROUT_RT, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_8B, N, N, N, DC, DC, DC, DC, DC),
LHZCIX -> List(U_LDST, LDST_LOAD, RA_RA_OR_ZERO, RB_RB, DC, ROUT_RT, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_2B, N, N, N, DC, DC, DC, DC, DC),
LWZCIX -> List(U_LDST, LDST_LOAD, RA_RA_OR_ZERO, RB_RB, DC, ROUT_RT, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_4B, N, N, N, DC, DC, DC, DC, DC),
STBCIX -> List(U_LDST, LDST_STORE, RA_RA_OR_ZERO, RB_RB, RS_RS, ROUT_NONE, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_1B, N, N, N, DC, DC, DC, DC, DC),
STDCIX -> List(U_LDST, LDST_STORE, RA_RA_OR_ZERO, RB_RB, RS_RS, ROUT_NONE, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_8B, N, N, N, DC, DC, DC, DC, DC),
STHCIX -> List(U_LDST, LDST_STORE, RA_RA_OR_ZERO, RB_RB, RS_RS, ROUT_NONE, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_2B, N, N, N, DC, DC, DC, DC, DC),
STWCIX -> List(U_LDST, LDST_STORE, RA_RA_OR_ZERO, RB_RB, RS_RS, ROUT_NONE, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_4B, N, N, N, DC, DC, DC, DC, DC),
LDX -> List(U_LDST, LDST_LOAD, RA_RA_OR_ZERO, RB_RB, DC, ROUT_RT, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_8B, N, N, N, DC, DC, DC, DC, DC),
LDUX -> List(U_LDST, LDST_LOAD, RA_RA_OR_ZERO, RB_RB, DC, ROUT_RT, CA_0, DC, DC, DC, CMP_RC_0, DC, N, N, DC, DC, DC, DC, LEN_8B, N, Y, N, DC, DC, DC, DC, DC),
STB -> List(U_LDST, LDST_STORE, RA_RA_OR_ZERO, RB_CONST_SI, RS_RS, ROUT_NONE, DC, DC, DC, DC, CMP_RC_0, DC, N, DC, DC, DC, DC, DC, LEN_1B, N, N, N, DC, DC, DC, DC, DC),