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Reformat toplevel.v

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2020-02-02 12:04:15 +11:00
committed by Anton Blanchard
parent c942fba2a9
commit ae8466e8de
1 changed files with 34 additions and 38 deletions
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72
toplevel.v
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@@ -1,49 +1,45 @@
module toplevel #(
parameter RESET_LOW = 1
parameter RESET_LOW = 1
) (
input clock,
input reset,
output io_tx,
input io_rx,
output io_terminate,
output io_ledB,
output io_ledC
input clock,
input reset,
output io_tx,
input io_rx,
output io_terminate,
output io_ledB,
output io_ledC
);
wire clock_out;
reg reset_out;
wire lock;
wire clock_out;
reg reset_out;
wire lock;
pll chiselwatt_pll(
.clki(clock),
.clko(clock_out),
.lock(lock)
);
pll chiselwatt_pll(
.clki(clock),
.clko(clock_out),
.lock(lock)
);
Core core(
.clock(clock_out),
.reset(reset_out),
.io_tx(io_tx),
.io_rx(io_rx),
.io_terminate(io_terminate),
.io_ledB(io_ledB),
.io_ledC(io_ledC)
);
Core core(
.clock(clock_out),
.reset(reset_out),
.io_tx(io_tx),
.io_rx(io_rx),
.io_terminate(io_terminate),
.io_ledB(io_ledB),
.io_ledC(io_ledC)
);
reg [21:0] cnt = ~0;
reg [21:0] cnt = ~0;
always@(posedge clock)
begin
if (~lock || (reset ^ RESET_LOW))
begin
cnt <= ~0;
end
else if (cnt != 0)
begin
cnt <= cnt - 1;
end
always@(posedge clock) begin
if (~lock || (reset ^ RESET_LOW)) begin
cnt <= ~0;
end else if (cnt != 0) begin
cnt <= cnt - 1;
end
reset_out <= |cnt;
end
reset_out <= |cnt;
end
endmodule