mirror of
https://github.com/antonblanchard/chiselwatt.git
synced 2026-01-13 07:20:14 +00:00
Rework core pipeline
For simplicity we originally made loads and stores slow instructions. We now want to integrate them into the fast pipeline, so add a new cycle to the pipeline (called memory). Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
Anton Blanchard
parent
121d967375
commit
bb295a6406
@ -14,6 +14,19 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
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val ledC = Output(UInt(1.W))
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})
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private def cmp(res: UInt, lt: Bool, is32bit: Bool): UInt = {
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val isZero = Mux(is32bit, res(31, 0) === 0.U, res === 0.U)
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val crLt = "b1000".U
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val crGt = "b0100".U
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val crZero = "b0010".U
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MuxCase(crGt, Seq(
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isZero -> crZero,
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lt -> crLt
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))
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}
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val memWords = memSize/(bits/8)
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val nia = Module(new Nia(bits, resetAddr))
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@ -61,6 +74,7 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
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val decodeNia = RegNext(nia.io.nia.bits)
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val decodeValid = RegNext(nia.io.nia.valid)
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// Decode
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control.io.insn := decodeInsn
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@ -102,12 +116,12 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
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val executeValid = RegNext(decodeValid)
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val executeNia = RegNext(decodeNia)
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// Execute
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val executeFastOp = MuxLookup(ctrl.unit, true.B, Array(
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val executeFast = MuxLookup(ctrl.unit, true.B, Array(
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U_MUL -> false.B,
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U_DIV -> false.B,
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U_LDST -> false.B
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U_DIV -> false.B
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))
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adder.io.a := executeRa
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@ -141,6 +155,20 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
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countZeroes.io.countRight := ctrl.countRight
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countZeroes.io.is32bit := ctrl.is32bit
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loadStore.io.in.bits.a := executeRa
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loadStore.io.in.bits.b := executeRb
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loadStore.io.in.bits.data := executeRs
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loadStore.io.in.bits.internalOp := ctrl.internalOp
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loadStore.io.in.bits.length := ctrl.length
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loadStore.io.in.bits.signed := ctrl.signed
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loadStore.io.in.bits.byteReverse := ctrl.byteReverse
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loadStore.io.in.bits.update := ctrl.update
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loadStore.io.in.bits.reservation := ctrl.reservation
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loadStore.io.in.valid := false.B
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when (executeValid && (ctrl.unit === U_LDST)) {
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loadStore.io.in.valid := true.B
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}
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multiplier.io.in.bits.a := executeRa
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multiplier.io.in.bits.b := executeRb
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multiplier.io.in.bits.is32bit := ctrl.is32bit
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@ -162,33 +190,19 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
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divider.io.in.valid := true.B
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}
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loadStore.io.in.bits.a := executeRa
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loadStore.io.in.bits.b := executeRb
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loadStore.io.in.bits.data := executeRs
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loadStore.io.in.bits.internalOp := ctrl.internalOp
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loadStore.io.in.bits.length := ctrl.length
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loadStore.io.in.bits.signed := ctrl.signed
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loadStore.io.in.bits.byteReverse := ctrl.byteReverse
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loadStore.io.in.bits.update := ctrl.update
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loadStore.io.in.bits.reservation := ctrl.reservation
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loadStore.io.in.valid := false.B
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when (executeValid && (ctrl.unit === U_LDST)) {
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loadStore.io.in.valid := true.B
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}
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val xerRegisterNum = 1
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val linkRegisterNum = 8
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val CountRegisterNum = 9
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val sprOut = RegInit(0.U(bits.W))
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val memSprOut = RegInit(0.U(bits.W))
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when (executeValid && (ctrl.unit === U_SPR)) {
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when (ctrl.internalOp === SPR_MF) {
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when (insn_spr(executeInsn) === linkRegisterNum.asUInt) {
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sprOut := linkRegister
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memSprOut := linkRegister
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} .elsewhen (insn_spr(executeInsn) === CountRegisterNum.asUInt) {
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sprOut := countRegister
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memSprOut := countRegister
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} .elsewhen (insn_spr(executeInsn) === xerRegisterNum.asUInt) {
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sprOut := carry << 29
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memSprOut := carry << 29
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} .otherwise {
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illegal := true.B
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}
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@ -205,7 +219,7 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
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}
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}
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val crOut = RegInit(0.U(bits.W))
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val memCrOut = RegInit(0.U(bits.W))
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when (executeValid && (ctrl.unit === U_CR)) {
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val fxm = WireDefault(UInt(8.W), 0.U)
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@ -219,7 +233,7 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
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}
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when (ctrl.internalOp === CR_MF) {
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crOut := fxm.asBools.zip(conditionRegister).map({ case (f, c) =>
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memCrOut := fxm.asBools.zip(conditionRegister).map({ case (f, c) =>
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Mux(f, c, 0.U)
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}).reduce(_ ## _)
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} .elsewhen (ctrl.internalOp === CR_MT) {
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@ -262,22 +276,23 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
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}
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}
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when (insn_lr(executeInsn).asBool) {
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linkRegister := executeNia + 4.U
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}
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when (branchTaken) {
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nia.io.redirect := true.B
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when (insn_lr(executeInsn).asBool) {
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linkRegister := executeNia + 4.U
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}
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}
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}
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val adderOut = RegNext(adder.io.out)
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val adderCarryOut = RegNext(adder.io.carryOut)
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val adderLtOut = RegNext(adder.io.ltOut.asBool)
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val logicalOut = RegNext(logical.io.out)
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val rotatorOut = RegNext(rotator.io.out)
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val rotatorCarryOut = RegNext(rotator.io.carryOut)
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val populationCountOut = RegNext(populationCount.io.out)
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val countZeroesOut = RegNext(countZeroes.io.out)
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val memAdderOut = RegNext(adder.io.out)
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val memAdderCarryOut = RegNext(adder.io.carryOut)
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val memAdderLtOut = RegNext(adder.io.ltOut.asBool)
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val memLogicalOut = RegNext(logical.io.out)
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val memRotatorOut = RegNext(rotator.io.out)
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val memRotatorCarryOut = RegNext(rotator.io.carryOut)
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val memPopulationCountOut = RegNext(populationCount.io.out)
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val memCountZeroesOut = RegNext(countZeroes.io.out)
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when (executeValid && (ctrl.unit === U_ILL)) {
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illegal := true.B
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@ -292,89 +307,120 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
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nia.io.redirect_nia := executeNia
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}
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/* Handle load and store with update instructions */
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val writebackLoadStoreAddr = RegNext(insn_ra(executeInsn))
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val writebackLoadStore = RegInit(false.B)
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writebackLoadStore := false.B
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val memValid = RegNext(executeValid)
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val memFast = RegNext(executeFast && executeValid)
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val memRegValid = RegNext(ctrl.rOut =/= ROUT_NONE)
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val memUnit = RegNext(ctrl.unit)
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val memRegAddr = RegNext(Mux(ctrl.rOut === ROUT_RA, insn_ra(executeInsn), insn_rt(executeInsn)))
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val memRcValid = RegNext((ctrl.compare === CMP_RC_1) || ((ctrl.compare === CMP_RC_RC) && insn_rc(executeInsn).asBool))
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val memCrValid = RegNext(ctrl.compare === CMP_CMP)
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val memCrAddr = RegNext(insn_bf(executeInsn))
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// Compare instructions need to know if a comparison is 32 bit
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val memIs32bit = RegNext(ctrl.is32bit.asBool)
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val memCarryValid = RegNext(ctrl.carryOut.asBool)
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/*
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* Handle load and store with update instructions. We rely on them being single issue
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* and we send the update directly to writeback, bypassing the mem cycle.
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*/
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val wbLoadStoreRegAddr = RegInit(insn_ra(executeInsn))
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val wbLoadStoreRegValid = Reg(Bool())
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wbLoadStoreRegValid := false.B
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when (executeValid && (ctrl.unit === U_LDST) && ctrl.update.asBool) {
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writebackLoadStore := true.B
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wbLoadStoreRegValid := true.B
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wbLoadStoreRegAddr := insn_ra(executeInsn)
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}
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val writebackFastValid = RegNext(executeValid && executeFastOp)
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val writebackFastCarryValid = RegNext(ctrl.carryOut.asBool)
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// Memory
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val memRegDataRc = MuxLookup(memUnit, memAdderOut, Array(
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U_LOG -> memLogicalOut,
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U_ROT -> memRotatorOut,
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U_ZER -> memCountZeroesOut,
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))
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val memRegData = MuxLookup(memUnit, memRegDataRc, Array(
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U_POP -> memPopulationCountOut,
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U_SPR -> memSprOut,
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U_CR -> memCrOut,
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))
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val memCarryData = MuxLookup(memUnit, memAdderCarryOut, Array(
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U_ROT -> memRotatorCarryOut
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))
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val memRcData = cmp(memRegDataRc, memRegDataRc(bits-1).asBool, false.B)
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when (memValid && memCrValid) {
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conditionRegister(memCrAddr) := cmp(memAdderOut, memAdderLtOut, memIs32bit)
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}
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val wbFast = RegNext(memFast)
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val wbCarryValid = RegNext(memCarryValid)
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val wbCarryData = RegNext(memCarryData)
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val wbRcData = RegNext(memRcData)
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// We need to gate these with executeValid because slow units need it
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val writebackUnit = RegInit(U_NONE)
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val writebackRValid = RegInit(false.B)
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val writebackAddr = RegInit(0.U)
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val writebackRc = RegInit(false.B)
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when (executeValid) {
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writebackUnit := ctrl.unit
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writebackRValid := ctrl.rOut =/= ROUT_NONE
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writebackAddr := Mux(ctrl.rOut === ROUT_RA, insn_ra(executeInsn), insn_rt(executeInsn))
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writebackRc := (ctrl.compare === CMP_RC_1) || ((ctrl.compare === CMP_RC_RC) && insn_rc(executeInsn).asBool)
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val wbUnit = RegInit(U_NONE)
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val wbRegValid = RegInit(false.B)
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val wbRegAddr = RegInit(0.U)
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val wbRcValid = RegInit(false.B)
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when (memValid) {
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wbRegValid := memRegValid
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wbUnit := memUnit
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wbRegAddr := memRegAddr
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wbRcValid := memRcValid
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}
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val writebackCmp = RegNext(ctrl.compare === CMP_CMP)
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val writebackCrField = RegNext(insn_bf(executeInsn))
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// Compare instructions need to know if a comparison is 32 bit
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val writebackIs32bit = RegNext(ctrl.is32bit.asBool)
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val wbRegData = RegNext(memRegData)
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// Writeback
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val wrRcData = MuxLookup(writebackUnit, adderOut, Array(
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U_LOG -> logicalOut,
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U_ROT -> rotatorOut,
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U_ZER -> countZeroesOut,
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val wbRegData1 = MuxLookup(wbUnit, multiplier.io.out.bits, Array(
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U_DIV -> divider.io.out.bits
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))
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val wbRegData2 = MuxLookup(wbUnit, wbRegData, Array(
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U_MUL -> multiplier.io.out.bits,
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U_DIV -> divider.io.out.bits,
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U_LDST -> loadStore.io.out.bits
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))
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val wrData = MuxLookup(writebackUnit, wrRcData, Array(
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U_POP -> populationCountOut,
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U_SPR -> sprOut,
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U_CR -> crOut,
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U_LDST -> loadStore.io.out.bits,
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val wbRcData1 = cmp(wbRegData1, wbRegData1(bits-1).asBool, false.B)
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val wbRcData2 = MuxLookup(wbUnit, wbRcData, Array(
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U_MUL -> wbRcData1,
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U_DIV -> wbRcData1
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))
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when (writebackLoadStore) {
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regFile.io.wr(0).bits.addr := writebackLoadStoreAddr
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regFile.io.wr(0).bits.data := adderOut
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when (wbFast && wbUnit === U_LDST) {
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assert(loadStore.io.out.valid)
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}
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when (wbLoadStoreRegValid) {
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regFile.io.wr(0).bits.addr := wbLoadStoreRegAddr
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regFile.io.wr(0).bits.data := memAdderOut
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regFile.io.wr(0).fire() := true.B
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}. otherwise {
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regFile.io.wr(0).bits.addr := writebackAddr
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regFile.io.wr(0).bits.data := wrData
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when (multiplier.io.out.valid || divider.io.out.valid || (loadStore.io.out.valid && writebackRValid)) {
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regFile.io.wr(0).fire() := true.B
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} .otherwise {
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regFile.io.wr(0).fire() := writebackFastValid && writebackRValid
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}
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regFile.io.wr(0).bits.addr := wbRegAddr
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regFile.io.wr(0).bits.data := wbRegData2
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regFile.io.wr(0).fire() := (wbFast && wbRegValid) || multiplier.io.out.valid || divider.io.out.valid
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}
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when (writebackFastValid && writebackFastCarryValid) {
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carry := MuxLookup(writebackUnit, adderCarryOut, Array(
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U_ROT -> rotatorCarryOut
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))
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when (wbFast && wbCarryValid) {
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carry := wbCarryData
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}
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private def cmp(res: UInt, lt: Bool, is32bit: Bool): UInt = {
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val isZero = Mux(is32bit, res(31, 0) === 0.U, res === 0.U)
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val crLt = "b1000".U
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val crGt = "b0100".U
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val crZero = "b0010".U
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MuxCase(crGt, Seq(
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isZero -> crZero,
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lt -> crLt
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))
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}
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when (writebackRc && (writebackFastValid || multiplier.io.out.valid || divider.io.out.valid)) {
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conditionRegister(0) := cmp(wrRcData, wrRcData(bits-1).asBool, false.B)
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} .elsewhen (writebackFastValid && writebackCmp) {
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conditionRegister(writebackCrField) :=
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cmp(adderOut, adderLtOut, writebackIs32bit)
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when (wbRcValid && (wbFast || multiplier.io.out.valid || divider.io.out.valid)) {
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conditionRegister(0) := wbRcData2
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}
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val sReset :: sFirst :: sRunning :: Nil = Enum(3)
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@ -389,7 +435,7 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
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}
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}
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val completed = RegNext((initState === sRunning) && (writebackFastValid || multiplier.io.out.valid || loadStore.io.out.valid || divider.io.out.valid))
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val completed = RegNext((initState === sRunning) && (wbFast || multiplier.io.out.valid || loadStore.io.out.valid || divider.io.out.valid))
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// One instruction in the entire pipeline at a time
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nia.io.nia.ready := completed || (initState === sFirst)
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@ -54,7 +54,7 @@ class LoadStore(val bits: Int, val words: Int) extends Module {
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val signed = Reg(UInt(1.W))
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val byteReverse = Reg(UInt(1.W))
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val reservation = Reg(UInt(1.W))
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val sIdle :: sStoreAccess :: sLoadFormat :: sLoadReturn :: Nil = Enum(4)
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val sIdle :: sStoreAccess :: sStoreIdle :: sLoadFormat :: sLoadReturn :: Nil = Enum(5)
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val state = RegInit(sIdle)
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val fifoLength = 128
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@ -126,6 +126,11 @@ class LoadStore(val bits: Int, val words: Int) extends Module {
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io.mem.writeData := data
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}
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/* Done, wait another cycle to line up with writeback */
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state := sStoreIdle
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}
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is (sStoreIdle) {
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/* Done */
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io.out.valid := true.B
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state := sIdle
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@ -52,6 +52,9 @@ class LoadStoreUnitTester extends FlatSpec with ChiselScalatestTester with Match
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m.clock.step()
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m.io.in.valid.poke(false.B)
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m.io.out.valid.expect(false.B)
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m.clock.step()
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m.io.out.valid.expect(true.B)
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m.clock.step()
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