mirror of
https://github.com/antonblanchard/chiselwatt.git
synced 2026-01-11 23:53:33 +00:00
Merge pull request #39 from carlosedp/polarfire
Add support for Microsemi Polarfire FPGA
This commit is contained in:
Anton Blanchard
GitHub
commit
c316067f33
@ -1,6 +1,6 @@
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CAPI=2:
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name : ::chiselwatt:0
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name: ::chiselwatt:0
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filesets:
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core:
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@ -8,81 +8,114 @@ filesets:
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- Core.v
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- MemoryBlackBox.v
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- toplevel.v
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- insns.hex : {copyto : insns.hex, file_type : user}
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file_type : verilogSource
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- insns.hex: { copyto: insns.hex, file_type: user }
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file_type: verilogSource
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helloworld:
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files:
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- samples/binaries/hello_world/hello_world.hex:
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{ copyto: insns.hex, file_type: user }
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micropython:
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files:
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- samples/binaries/micropython/firmware.hex:
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{ copyto: insns.hex, file_type: user }
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cmod_a7-35:
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files:
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- constraints/cmod_a7-35.xdc : {file_type : xdc}
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- pll/pll_mmcme2.v : {file_type : verilogSource}
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- constraints/cmod_a7-35.xdc: { file_type: xdc }
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- pll/pll_mmcme2.v: { file_type: verilogSource }
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arty_a7:
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files:
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- constraints/arty_a7.xdc : {file_type : xdc}
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- pll/pll_bypass.v : {file_type : verilogSource}
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- constraints/arty_a7.xdc: { file_type: xdc }
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- pll/pll_bypass.v: { file_type: verilogSource }
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nexys_video:
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files:
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- constraints/nexys-video.xdc : {file_type : xdc}
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- pll/pll_bypass.v : {file_type : verilogSource}
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- constraints/nexys-video.xdc: { file_type: xdc }
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- pll/pll_bypass.v: { file_type: verilogSource }
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ecp5-evn:
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files:
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- constraints/ecp5-evn.lpf : {file_type : LPF}
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- pll/pll_ehxplll.v : {file_type : verilogSource}
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- constraints/ecp5-evn.lpf: { file_type: LPF }
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- pll/pll_ehxplll.v: { file_type: verilogSource }
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ecp5-ulx3s:
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files:
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- constraints/ecp5-ulx3s.lpf : {file_type : LPF}
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- pll/pll_ehxplll_25MHz.v : {file_type : verilogSource}
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- constraints/ecp5-ulx3s.lpf: { file_type: LPF }
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- pll/pll_ehxplll_25MHz.v: { file_type: verilogSource }
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polarfireeval:
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files:
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- constraints/polarfire_eval.pdc: { file_type: PDC }
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- pll/pll_polarfire50MHz.v: { file_type: verilogSource }
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targets:
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cmod_a7-35:
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default_tool: vivado
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filesets: [core, cmod_a7-35]
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parameters :
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parameters:
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- RESET_LOW=false
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tools:
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vivado: {part : xc7a35tcpg236-1}
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toplevel : toplevel
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vivado: { part: xc7a35tcpg236-1 }
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toplevel: toplevel
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arty_a7-35:
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default_tool: vivado
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filesets: [core, arty_a7]
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tools:
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vivado: {part : xc7a35ticsg324-1L}
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toplevel : toplevel
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vivado: { part: xc7a35ticsg324-1L }
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toplevel: toplevel
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arty_a7-100:
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default_tool: vivado
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filesets: [core, arty_a7]
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tools:
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vivado: {part : xc7a100ticsg324-1L}
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toplevel : toplevel
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vivado: { part: xc7a100ticsg324-1L }
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toplevel: toplevel
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nexys_video:
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default_tool: vivado
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filesets: [core, nexys_video]
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tools:
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vivado: {part : xc7a200tsbg484-1}
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toplevel : toplevel
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vivado: { part: xc7a200tsbg484-1 }
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toplevel: toplevel
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ecp5-evn:
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default_tool: diamond
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filesets: [core, ecp5-evn]
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tools:
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diamond: {part: LFE5U-85F-8BG381I}
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toplevel : toplevel
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diamond: { part: LFE5U-85F-8BG381I }
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toplevel: toplevel
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ecp5-ulx3s:
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default_tool: diamond
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filesets: [core, ecp5-ulx3s]
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tools:
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diamond: {part: LFE5U-85F-8BG381I}
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toplevel : toplevel
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diamond: { part: LFE5U-85F-8BG381I }
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toplevel: toplevel
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polarfireeval: &polarfireeval
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default_tool: libero
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description: Microsemi Polarfire Evaluation Kit
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filesets: [core, polarfireeval, micropython]
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tools:
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libero: &liberoMPF300
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family: PolarFire
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die: MPF300TS
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package: FCG1152
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toplevel: toplevel
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polarfireeval_es:
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<<: *polarfireeval
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tools:
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libero:
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<<: *liberoMPF300
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die: MPF300TS_ES
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parameters:
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RESET_LOW:
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datatype : bool
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description : External reset button polarity
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paramtype : generic
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datatype: bool
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description: External reset button polarity
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paramtype: generic
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9
constraints/polarfire_eval.pdc
Normal file
9
constraints/polarfire_eval.pdc
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@ -0,0 +1,9 @@
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set_io -port_name {clock} -pin_name E25 -io_std LVCMOS18 -fixed true
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set_io -port_name {reset} -pin_name K22 -io_std LVCMOS18 -fixed true
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set_io -port_name {io_tx} -pin_name G17 -io_std LVCMOS18 -fixed true
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set_io -port_name {io_rx} -pin_name H18 -io_std LVCMOS18 -fixed true
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set_io -port_name {io_terminate} -pin_name F22 -io_std LVCMOS18 -fixed true
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set_io -port_name {io_ledB} -pin_name B26 -io_std LVCMOS18 -fixed true
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set_io -port_name {io_ledC} -pin_name C26 -io_std LVCMOS18 -fixed true
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@ -1,4 +1,4 @@
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module pll(
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module Chiselwatt_pll(
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input clki,
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output reg clko,
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output reg lock
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@ -1,4 +1,4 @@
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module pll(
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module Chiselwatt_pll(
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input clki,
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output clko,
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output lock
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@ -1,4 +1,4 @@
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module pll(
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module Chiselwatt_pll(
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input clki,
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output clko,
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output lock
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@ -1,4 +1,4 @@
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module pll(
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module Chiselwatt_pll(
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input clki,
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output clko,
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output lock
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66
pll/pll_polarfire50MHz.v
Normal file
66
pll/pll_polarfire50MHz.v
Normal file
@ -0,0 +1,66 @@
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`timescale 1 ns/100 ps
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// Version: v12.5 12.900.10.16
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module Chiselwatt_pll(
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clki,
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lock,
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clko
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);
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output clko;
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output lock;
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input clki;
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wire gnd_net, vcc_net, pll_inst_0_clkint_0;
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CLKINT clkint_0 (.A(pll_inst_0_clkint_0), .Y(clko));
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PLL #( .VCOFREQUENCY(5000), .DELAY_LINE_SIMULATION_MODE(""), .DATA_RATE(0.0)
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, .FORMAL_NAME(""), .INTERFACE_NAME(""), .INTERFACE_LEVEL(3'b0)
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, .SOFTRESET(1'b0), .SOFT_POWERDOWN_N(1'b1), .RFDIV_EN(1'b1), .OUT0_DIV_EN(1'b1)
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, .OUT1_DIV_EN(1'b0), .OUT2_DIV_EN(1'b0), .OUT3_DIV_EN(1'b0), .SOFT_REF_CLK_SEL(1'b0)
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, .RESET_ON_LOCK(1'b1), .BYPASS_CLK_SEL(4'b0), .BYPASS_GO_EN_N(1'b1)
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, .BYPASS_PLL(4'b0), .BYPASS_OUT_DIVIDER(4'b0), .FF_REQUIRES_LOCK(1'b0)
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, .FSE_N(1'b0), .FB_CLK_SEL_0(2'b00), .FB_CLK_SEL_1(1'b0), .RFDIV(6'b000001)
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, .FRAC_EN(1'b0), .FRAC_DAC_EN(1'b0), .DIV0_RST_DELAY(3'b000)
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, .DIV0_VAL(7'b0011001), .DIV1_RST_DELAY(3'b0), .DIV1_VAL(7'b1)
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, .DIV2_RST_DELAY(3'b0), .DIV2_VAL(7'b1), .DIV3_RST_DELAY(3'b0)
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, .DIV3_VAL(7'b1), .DIV3_CLK_SEL(1'b0), .BW_INT_CTRL(2'b0), .BW_PROP_CTRL(2'b01)
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, .IREF_EN(1'b1), .IREF_TOGGLE(1'b0), .LOCK_CNT(4'b1000), .DESKEW_CAL_CNT(3'b110)
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, .DESKEW_CAL_EN(1'b1), .DESKEW_CAL_BYPASS(1'b0), .SYNC_REF_DIV_EN(1'b0)
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, .SYNC_REF_DIV_EN_2(1'b0), .OUT0_PHASE_SEL(3'b000), .OUT1_PHASE_SEL(3'b0)
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, .OUT2_PHASE_SEL(3'b0), .OUT3_PHASE_SEL(3'b0), .SOFT_LOAD_PHASE_N(1'b1)
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, .SSM_DIV_VAL(6'b1), .FB_FRAC_VAL(24'b0), .SSM_SPREAD_MODE(1'b0)
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, .SSM_MODULATION(5'b00101), .FB_INT_VAL(12'b000001100100), .SSM_EN_N(1'b1)
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, .SSM_EXT_WAVE_EN(2'b0), .SSM_EXT_WAVE_MAX_ADDR(8'b0), .SSM_RANDOM_EN(1'b0)
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, .SSM_RANDOM_PATTERN_SEL(3'b0), .CDMUX0_SEL(2'b0), .CDMUX1_SEL(1'b1)
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, .CDMUX2_SEL(1'b0), .CDELAY0_SEL(8'b0), .CDELAY0_EN(1'b0), .DRI_EN(1'b1)
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) pll_inst_0 (.LOCK(lock), .SSCG_WAVE_TABLE_ADDR({nc0,
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nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .DELAY_LINE_OUT_OF_RANGE()
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, .POWERDOWN_N(vcc_net), .OUT0_EN(vcc_net), .OUT1_EN(gnd_net),
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.OUT2_EN(gnd_net), .OUT3_EN(gnd_net), .REF_CLK_SEL(gnd_net),
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.BYPASS_EN_N(vcc_net), .LOAD_PHASE_N(vcc_net),
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.SSCG_WAVE_TABLE({gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net, gnd_net, gnd_net}), .PHASE_DIRECTION(gnd_net),
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.PHASE_ROTATE(gnd_net), .PHASE_OUT0_SEL(gnd_net),
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.PHASE_OUT1_SEL(gnd_net), .PHASE_OUT2_SEL(gnd_net),
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.PHASE_OUT3_SEL(gnd_net), .DELAY_LINE_MOVE(gnd_net),
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.DELAY_LINE_DIRECTION(gnd_net), .DELAY_LINE_WIDE(gnd_net),
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.DELAY_LINE_LOAD(vcc_net), .REFCLK_SYNC_EN(gnd_net),
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.REF_CLK_0(clki), .REF_CLK_1(gnd_net), .FB_CLK(gnd_net),
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.OUT0(pll_inst_0_clkint_0), .OUT1(), .OUT2(), .OUT3(),
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.DRI_CLK(gnd_net), .DRI_CTRL({gnd_net, gnd_net, gnd_net,
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net}), .DRI_WDATA({gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net}), .DRI_ARST_N(vcc_net), .DRI_RDATA({nc8, nc9, nc10,
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nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20,
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nc21, nc22, nc23, nc24, nc25, nc26, nc27, nc28, nc29, nc30,
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nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40}),
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.DRI_INTERRUPT());
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VCC vcc_inst (.Y(vcc_net));
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GND gnd_inst (.Y(gnd_net));
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endmodule
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@ -14,7 +14,7 @@ module toplevel #(
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reg reset_out;
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wire lock;
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pll chiselwatt_pll(
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Chiselwatt_pll chiselwatt_pll(
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.clki(clock),
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.clko(clock_out),
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.lock(lock)
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