mirror of
https://github.com/antonblanchard/chiselwatt.git
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FuseSoC Nexys Video support
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
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parent
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@ -21,6 +21,11 @@ filesets:
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- constraints/arty_a7.xdc : {file_type : xdc}
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- pll/pll_bypass.v : {file_type : verilogSource}
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nexys_video:
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files:
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- constraints/nexys-video.xdc : {file_type : xdc}
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- pll/pll_bypass.v : {file_type : verilogSource}
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ecp5-evn:
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files:
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- constraints/ecp5-evn.lpf : {file_type : LPF}
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@ -50,6 +55,13 @@ targets:
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vivado: {part : xc7a100ticsg324-1L}
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toplevel : toplevel
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nexys_video:
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default_tool: vivado
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filesets: [core, nexys_video]
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tools:
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vivado: {part : xc7a200tsbg484-1}
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toplevel : toplevel
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ecp5-evn:
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default_tool: diamond
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filesets: [core, ecp5-evn]
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19
constraints/nexys-video.xdc
Normal file
19
constraints/nexys-video.xdc
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@ -0,0 +1,19 @@
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set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports clock]
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create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clock]
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set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports reset]
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set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports io_tx]
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set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports io_rx]
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set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS25 } [get_ports { io_terminate }]
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set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS25 } [get_ports { io_ledB }]
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set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS25 } [get_ports { io_ledC }]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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