mirror of
https://github.com/antonblanchard/chiselwatt.git
synced 2026-03-06 11:24:02 +00:00
20 lines
920 B
Tcl
20 lines
920 B
Tcl
set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports clock]
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create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clock]
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set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports reset]
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set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports io_tx]
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set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports io_rx]
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set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS25 } [get_ports { io_terminate }]
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set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS25 } [get_ports { io_ledB }]
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set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS25 } [get_ports { io_ledC }]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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