1
0
mirror of https://github.com/antonblanchard/microwatt.git synced 2026-02-28 17:19:06 +00:00

Default Branch

efd0571b5f · Merge pull request #461 from paulusmack/master · Updated 2026-02-04 23:05:42 +00:00

Branches

2083bc3ed0 · ASIC: Fix multiplier power · Updated 2022-06-06 22:50:35 +00:00

451
15

907c833521 · Move register stage back after the RAM · Updated 2022-03-23 06:43:09 +00:00

451
13

5c40143754 · Add a script to post process the Microwatt verilog for caravel · Updated 2022-03-21 23:29:12 +00:00

451
12

948f6f43a7 · Allow ALT_RESET_ADDRESS to be overridden · Updated 2022-03-21 22:35:17 +00:00

450
0
Included

b5accb78b2 · wishbone_bram_wrapper ram_addr_bits is 1 bit off · Updated 2022-03-17 07:10:36 +00:00

452
0
Included

50b4cb9423 · fpu: Make inverse_table a constant · Updated 2022-03-15 05:03:34 +00:00

458
0
Included

11c5ac68e8 · Fix caravel script · Updated 2022-02-01 10:03:56 +00:00

481
16

ceb15d3ca8 · Hack to test under verilator · Updated 2021-10-10 23:01:23 +00:00

504
2

2d142a6c01 · tests/misc: Add a store/dcbz test · Updated 2021-09-27 05:30:41 +00:00

509
0
Included

06266fe84a · Orange Crab is 48MHz not 50MHz, bump PLL frequency · Updated 2021-09-24 02:43:33 +00:00

528
0
Included

b29c58f3d1 · dcache: Loads from non-cacheable PTEs load entire 64 bits · Updated 2021-09-10 10:51:53 +00:00

539
0
Included

1d29cdcfb4 · Remove Potato UART · Updated 2021-08-11 08:42:14 +00:00

565
1

53ccf89d26 · Use a record for cache parameters · Updated 2021-03-23 00:37:50 +00:00

646
1

f3f159c6dc · Check in verilog · Updated 2021-01-13 23:54:27 +00:00

701
24

3da9642020 · Check in verilog · Updated 2021-01-05 09:27:47 +00:00

698
21

ab2c87a161 · Update JTAG TAP controller for Microwatt · Updated 2020-12-09 07:05:50 +00:00

712
2

6dbc7c0559 · Update JTAG TAP controller for Microwatt · Updated 2020-12-08 10:36:47 +00:00

712
2

986881f258 · Add a patch to route the NIA out to GPIOs · Updated 2019-09-12 06:53:09 +00:00

1422
1