Use a record for cache parameters

The number of generics we pass down from the top level is getting a
bit unwieldy. Paul suggests using records to group them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

Makefile

@@ -41,7 +41,7 @@ all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
 
 all: $(all)
 
-core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
+core_files = params.vhdl decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
 	utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
 	decode1.vhdl helpers.vhdl insn_helpers.vhdl \
 	control.vhdl decode2.vhdl register_file.vhdl \

core.vhdl

@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 library work;
+use work.params.all;
 use work.common.all;
 use work.wishbone_types.all;
 
@@ -15,13 +16,7 @@ entity core is
         HAS_BTC : boolean := true;
 	ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
         LOG_LENGTH : natural := 512;
-        ICACHE_NUM_LINES : natural := 64;
-        ICACHE_NUM_WAYS : natural := 2;
-        ICACHE_TLB_SIZE : natural := 64;
-        DCACHE_NUM_LINES : natural := 64;
-        DCACHE_NUM_WAYS : natural := 2;
-        DCACHE_TLB_SET_SIZE : natural := 64;
-        DCACHE_TLB_NUM_WAYS : natural := 2
+        CACHE_PARAMS : CACHE_PARAMS_T := CACHE_PARAMS_DEFAULT
         );
     port (
         clk          : in std_ulogic;
@@ -223,10 +218,10 @@ begin
     icache_0: entity work.icache
         generic map(
             SIM => SIM,
-            LINE_SIZE => 64,
-            NUM_LINES => ICACHE_NUM_LINES,
-            NUM_WAYS => ICACHE_NUM_WAYS,
-            TLB_SIZE => ICACHE_TLB_SIZE,
+            LINE_SIZE => CACHE_PARAMS.LINE_SIZE,
+            NUM_LINES => CACHE_PARAMS.ICACHE_NUM_LINES,
+            NUM_WAYS => CACHE_PARAMS.ICACHE_NUM_WAYS,
+            TLB_SIZE => CACHE_PARAMS.ICACHE_TLB_SIZE,
             LOG_LENGTH => LOG_LENGTH
             )
         port map(
@@ -406,11 +401,11 @@ begin
 
     dcache_0: entity work.dcache
         generic map(
-            LINE_SIZE => 64,
-            NUM_LINES => DCACHE_NUM_LINES,
-            NUM_WAYS => DCACHE_NUM_WAYS,
-            TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
-            TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS,
+            LINE_SIZE => CACHE_PARAMS.LINE_SIZE,
+            NUM_LINES => CACHE_PARAMS.DCACHE_NUM_LINES,
+            NUM_WAYS => CACHE_PARAMS.DCACHE_NUM_WAYS,
+            TLB_SET_SIZE => CACHE_PARAMS.DCACHE_TLB_SET_SIZE,
+            TLB_NUM_WAYS => CACHE_PARAMS.DCACHE_TLB_NUM_WAYS,
             LOG_LENGTH => LOG_LENGTH
             )
         port map (

microwatt.core

@@ -5,6 +5,7 @@ name : ::microwatt:0
 filesets:
   core:
     files:
+      - params.vhdl
       - decode_types.vhdl
       - wishbone_types.vhdl
       - common.vhdl

params.vhdl

@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package params is
+    type CACHE_PARAMS_T is record
+        LINE_SIZE           : natural;
+        ICACHE_NUM_LINES    : natural;
+        ICACHE_NUM_WAYS     : natural;
+        ICACHE_TLB_SIZE     : natural;
+        DCACHE_NUM_LINES    : natural;
+        DCACHE_NUM_WAYS     : natural;
+        DCACHE_TLB_SET_SIZE : natural;
+        DCACHE_TLB_NUM_WAYS : natural;
+    end record;
+
+    constant CACHE_PARAMS_DEFAULT : CACHE_PARAMS_T := (
+        LINE_SIZE           => 64,
+        ICACHE_NUM_LINES    => 64,
+        ICACHE_NUM_WAYS     => 2,
+        ICACHE_TLB_SIZE     => 64,
+        DCACHE_NUM_LINES    => 64,
+        DCACHE_NUM_WAYS     => 2,
+        DCACHE_TLB_SET_SIZE => 64,
+        DCACHE_TLB_NUM_WAYS => 2
+    );
+
+end package;

soc.vhdl

@@ -6,6 +6,7 @@ use std.textio.all;
 use std.env.stop;
 
 library work;
+use work.params.all;
 use work.common.all;
 use work.wishbone_types.all;
 
@@ -67,13 +68,7 @@ entity soc is
         HAS_LITEETH        : boolean := false;
 	UART0_IS_16550     : boolean := true;
 	HAS_UART1          : boolean := false;
-        ICACHE_NUM_LINES   : natural := 64;
-        ICACHE_NUM_WAYS    : natural := 2;
-        ICACHE_TLB_SIZE    : natural := 64;
-        DCACHE_NUM_LINES   : natural := 64;
-        DCACHE_NUM_WAYS    : natural := 2;
-        DCACHE_TLB_SET_SIZE : natural := 64;
-        DCACHE_TLB_NUM_WAYS : natural := 2
+        CACHE_PARAMS       : CACHE_PARAMS_T := CACHE_PARAMS_DEFAULT
 	);
     port(
 	rst          : in  std_ulogic;
@@ -267,13 +262,7 @@ begin
 	    DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
 	    ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
             LOG_LENGTH => LOG_LENGTH,
-            ICACHE_NUM_LINES => ICACHE_NUM_LINES,
-            ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
-            ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
-            DCACHE_NUM_LINES => DCACHE_NUM_LINES,
-            DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
-            DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
-            DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
+            CACHE_PARAMS => CACHE_PARAMS
 	    )
 	port map(
 	    clk => system_clk,