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Move register stage from after RAM to before RAM

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
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Anton Blanchard
2022-02-24 10:18:28 +11:00
parent 52f2462232
commit 01f8ad55ef
1 changed files with 17 additions and 8 deletions
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25
asic/main_bram.vhdl
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@@ -34,30 +34,39 @@ architecture behaviour of main_bram is
signal sel_qual: std_ulogic_vector((WIDTH/8)-1 downto 0);
signal obuf : std_logic_vector(WIDTH-1 downto 0);
signal addr_buf : std_logic_vector(HEIGHT_BITS-1 downto 0);
signal din_buf : std_logic_vector(WIDTH-1 downto 0);
signal sel_buf : std_logic_vector((WIDTH/8)-1 downto 0);
signal re_buf : std_ulogic;
signal we_buf : std_ulogic;
begin
assert (WIDTH = 64) report "Must be 64 bit" severity FAILURE;
-- Do we have a log2 round up issue here?
assert (HEIGHT_BITS = 9) report "HEIGHT_BITS must be 10" severity FAILURE;
assert (MEMORY_SIZE = 4096) report "MEMORY_SIZE must be 4096" severity FAILURE;
sel_qual <= sel when we = '1' else (others => '0');
sel_qual <= sel_buf when we_buf = '1' else (others => '0');
memory_0 : RAM512
port map (
CLK => clk,
WE0 => sel_qual(7 downto 0),
EN0 => re or we,
Di0 => din(63 downto 0),
Do0 => obuf(63 downto 0),
A0 => addr(8 downto 0)
EN0 => re_buf or we_buf,
Di0 => din_buf(63 downto 0),
Do0 => dout(63 downto 0),
A0 => addr_buf(8 downto 0)
);
-- The wishbone BRAM wrapper assumes a 1 cycle delay
-- The wishbone BRAM wrapper assumes a 1 cycle delay.
-- Since the DFFRAM already registers outputs, place this on the input side.
memory_read_buffer: process(clk)
begin
if rising_edge(clk) then
dout <= obuf;
addr_buf <= addr;
din_buf <= din;
sel_buf <= sel;
re_buf <= re;
we_buf <= we;
end if;
end process;
end architecture behaviour;