mirror of
https://github.com/antonblanchard/microwatt.git
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FPU: Implement floating convert to integer instructions
This implements fctiw, fctiwz, fctiwu, fctiwuz, fctid, fctidz, fctidu and fctiduz, and adds tests for them. There are some subtleties around the setting of the inexact (XX) and invalid conversion (VXCVI) flags in the FPSCR. If the rounded value ends up being out of range, we need to set VXCVI and not XX. For a conversion to unsigned word or doubleword of a negative value that rounds to zero, we need to set XX and not VXCVI. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
@@ -442,8 +442,16 @@ architecture behaviour of decode1 is
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2#100000100# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 4/8=fnabs
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2#100001000# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 8/8=fabs
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2#110000000# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- 0/12=frsp
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2#111000000# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 0/14=fctiw
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2#111000100# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 4/14=fctiwu
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2#111011001# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 25/14=fctid
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2#111011010# => (FPU, OP_FPOP_I, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 26/14=fcfid
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2#111011101# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 29/14=fctidu
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2#111011110# => (FPU, OP_FPOP_I, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 30/14=fcfidu
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2#111100000# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 0/15=fctiwz
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2#111100100# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 4/15=fctiwuz
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2#111111001# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 25/15=fctidz
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2#111111101# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- 29/15=fctiduz
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others => illegal_inst
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);
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157
fpu.vhdl
157
fpu.vhdl
@@ -38,8 +38,10 @@ architecture behaviour of fpu is
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type state_t is (IDLE,
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DO_MCRFS, DO_MTFSB, DO_MTFSFI, DO_MFFS, DO_MTFSF,
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DO_FMR,
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DO_FCFID,
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DO_FCFID, DO_FCTI,
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DO_FRSP,
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INT_SHIFT, INT_ROUND, INT_ISHIFT,
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INT_FINAL, INT_CHECK, INT_OFLOW,
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FINISH, NORMALIZE,
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ROUND_UFLOW, ROUND_OFLOW,
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ROUNDING, ROUNDING_2, ROUNDING_3,
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@@ -363,6 +365,8 @@ begin
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variable clz : std_ulogic_vector(5 downto 0);
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variable set_x : std_ulogic;
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variable mshift : signed(EXP_BITS-1 downto 0);
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variable need_check : std_ulogic;
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variable msb : std_ulogic;
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begin
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v := r;
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illegal := '0';
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@@ -461,8 +465,15 @@ begin
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when "01100" =>
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v.state := DO_FRSP;
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when "01110" =>
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-- fcfid[u][s]
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v.state := DO_FCFID;
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if int_input = '1' then
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-- fcfid[u][s]
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v.state := DO_FCFID;
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else
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v.state := DO_FCTI;
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end if;
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when "01111" =>
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v.round_mode := "001";
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v.state := DO_FCTI;
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when others =>
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illegal := '1';
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end case;
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@@ -603,6 +614,47 @@ begin
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arith_done := '1';
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end if;
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when DO_FCTI =>
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-- instr bit 9: 1=dword 0=word
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-- instr bit 8: 1=unsigned 0=signed
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-- instr bit 1: 1=round to zero 0=use fpscr[RN]
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opsel_a <= AIN_B;
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v.result_class := r.b.class;
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v.result_sign := r.b.negative;
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v.result_exp := r.b.exponent;
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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if r.b.class = NAN and r.b.mantissa(53) = '0' then
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-- Signalling NAN
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v.fpscr(FPSCR_VXSNAN) := '1';
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invalid := '1';
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end if;
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v.int_result := '1';
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case r.b.class is
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when ZERO =>
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arith_done := '1';
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when FINITE =>
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if r.b.exponent >= to_signed(64, EXP_BITS) or
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(r.insn(9) = '0' and r.b.exponent >= to_signed(32, EXP_BITS)) then
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v.state := INT_OFLOW;
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elsif r.b.exponent >= to_signed(52, EXP_BITS) then
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-- integer already, no rounding required,
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-- shift into final position
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v.shift := r.b.exponent - to_signed(54, EXP_BITS);
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if r.insn(8) = '1' and r.b.negative = '1' then
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v.state := INT_OFLOW;
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else
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v.state := INT_ISHIFT;
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end if;
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else
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v.shift := r.b.exponent - to_signed(52, EXP_BITS);
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v.state := INT_SHIFT;
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end if;
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when INFINITY | NAN =>
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v.state := INT_OFLOW;
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end case;
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when DO_FCFID =>
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v.result_sign := '0';
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opsel_a <= AIN_B;
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@@ -622,6 +674,81 @@ begin
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v.state := FINISH;
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end if;
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when INT_SHIFT =>
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opsel_r <= RES_SHIFT;
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set_x := '1';
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v.state := INT_ROUND;
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v.shift := to_signed(-2, EXP_BITS);
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when INT_ROUND =>
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opsel_r <= RES_SHIFT;
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round := fp_rounding(r.r, r.x, '0', r.round_mode, r.result_sign);
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v.fpscr(FPSCR_FR downto FPSCR_FI) := round;
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-- Check for negative values that don't round to 0 for fcti*u*
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if r.insn(8) = '1' and r.result_sign = '1' and
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(r_hi_nz or r_lo_nz or v.fpscr(FPSCR_FR)) = '1' then
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v.state := INT_OFLOW;
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else
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v.state := INT_FINAL;
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end if;
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when INT_ISHIFT =>
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opsel_r <= RES_SHIFT;
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v.state := INT_FINAL;
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when INT_FINAL =>
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-- Negate if necessary, and increment for rounding if needed
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opsel_ainv <= r.result_sign;
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carry_in <= r.fpscr(FPSCR_FR) xor r.result_sign;
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-- Check for possible overflows
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case r.insn(9 downto 8) is
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when "00" => -- fctiw[z]
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need_check := r.r(31) or (r.r(30) and not r.result_sign);
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when "01" => -- fctiwu[z]
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need_check := r.r(31);
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when "10" => -- fctid[z]
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need_check := r.r(63) or (r.r(62) and not r.result_sign);
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when others => -- fctidu[z]
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need_check := r.r(63);
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end case;
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if need_check = '1' then
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v.state := INT_CHECK;
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else
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if r.fpscr(FPSCR_FI) = '1' then
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v.fpscr(FPSCR_XX) := '1';
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end if;
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arith_done := '1';
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end if;
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when INT_CHECK =>
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if r.insn(9) = '0' then
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msb := r.r(31);
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else
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msb := r.r(63);
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end if;
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misc_sel <= '1' & r.insn(9 downto 8) & r.result_sign;
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if (r.insn(8) = '0' and msb /= r.result_sign) or
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(r.insn(8) = '1' and msb /= '1') then
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opsel_r <= RES_MISC;
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v.fpscr(FPSCR_VXCVI) := '1';
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invalid := '1';
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else
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if r.fpscr(FPSCR_FI) = '1' then
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v.fpscr(FPSCR_XX) := '1';
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end if;
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end if;
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arith_done := '1';
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when INT_OFLOW =>
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opsel_r <= RES_MISC;
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misc_sel <= '1' & r.insn(9 downto 8) & r.result_sign;
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if r.b.class = NAN then
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misc_sel(0) <= '1';
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end if;
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v.fpscr(FPSCR_VXCVI) := '1';
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invalid := '1';
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arith_done := '1';
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when FINISH =>
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if r.r(63 downto 54) /= "0000000001" then
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renormalize := '1';
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@@ -846,6 +973,30 @@ begin
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when "0011" =>
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-- mantissa of max representable SP number
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misc := x"007fffff80000000";
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when "1000" =>
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-- max positive result for fctiw[z]
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misc := x"000000007fffffff";
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when "1001" =>
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-- max negative result for fctiw[z]
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misc := x"ffffffff80000000";
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when "1010" =>
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-- max positive result for fctiwu[z]
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misc := x"00000000ffffffff";
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when "1011" =>
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-- max negative result for fctiwu[z]
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misc := x"0000000000000000";
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when "1100" =>
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-- max positive result for fctid[z]
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misc := x"7fffffffffffffff";
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when "1101" =>
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-- max negative result for fctid[z]
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misc := x"8000000000000000";
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when "1110" =>
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-- max positive result for fctidu[z]
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misc := x"ffffffffffffffff";
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when "1111" =>
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-- max negative result for fctidu[z]
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misc := x"0000000000000000";
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when others =>
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misc := x"0000000000000000";
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end case;
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157
tests/fpu/fpu.c
157
tests/fpu/fpu.c
@@ -19,6 +19,7 @@
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#define FPS_UE 0x20
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#define FPS_OE 0x40
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#define FPS_VE 0x80
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#define FPS_VXCVI 0x100
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#define FPS_VXSOFT 0x400
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extern int trapit(long arg, int (*func)(long));
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@@ -598,6 +599,160 @@ int fpu_test_8(void)
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return trapit(0, test8);
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}
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struct cvtivals {
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unsigned long dval;
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long lval;
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unsigned long ulval;
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int ival;
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unsigned int uival;
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unsigned char invalids[4];
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} cvtivals[] = {
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{ 0x0000000000000000, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x8000000000000000, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x3fdfffffffffffff, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x3ff0000000000000, 1, 1, 1, 1, {0, 0, 0, 0} },
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{ 0xbff0000000000000, -1, 0, -1, 0, {0, 1, 0, 1} },
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{ 0x402123456789abcd, 9, 9, 9, 9, {0, 0, 0, 0} },
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{ 0x406123456789abcd, 137, 137, 137, 137, {0, 0, 0, 0} },
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{ 0x409123456789abcd, 1097, 1097, 1097, 1097, {0, 0, 0, 0} },
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{ 0x41c123456789abcd, 0x22468acf, 0x22468acf, 0x22468acf, 0x22468acf, {0, 0, 0, 0} },
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{ 0x41d123456789abcd, 0x448d159e, 0x448d159e, 0x448d159e, 0x448d159e, {0, 0, 0, 0} },
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{ 0x41e123456789abcd, 0x891a2b3c, 0x891a2b3c, 0x7fffffff, 0x891a2b3c, {0, 0, 1, 0} },
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{ 0x41f123456789abcd, 0x112345679, 0x112345679, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0xc1f123456789abcd, -0x112345679, 0, 0x80000000, 0, {0, 1, 1, 1} },
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{ 0x432123456789abcd, 0x891a2b3c4d5e6, 0x891a2b3c4d5e6, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x433123456789abcd, 0x1123456789abcd, 0x1123456789abcd, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x434123456789abcd, 0x22468acf13579a, 0x22468acf13579a, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x43c123456789abcd, 0x22468acf13579a00, 0x22468acf13579a00, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x43d123456789abcd, 0x448d159e26af3400, 0x448d159e26af3400, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x43e123456789abcd, 0x7fffffffffffffff, 0x891a2b3c4d5e6800, 0x7fffffff, 0xffffffff, {1, 0, 1, 1} },
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{ 0x43f123456789abcd, 0x7fffffffffffffff, 0xffffffffffffffff, 0x7fffffff, 0xffffffff, {1, 1, 1, 1} },
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{ 0xc3f123456789abcd, 0x8000000000000000, 0, 0x80000000, 0, {1, 1, 1, 1} },
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{ 0x7ff0000000000000, 0x7fffffffffffffff, 0xffffffffffffffff, 0x7fffffff, 0xffffffff, {1, 1, 1, 1} },
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{ 0xfff0000000000000, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
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{ 0x7ff923456789abcd, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
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{ 0xfff923456789abcd, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
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{ 0xbfd123456789abcd, 0, 0, 0, 0, {0, 0, 0, 0} },
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};
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#define GET_VXCVI() ((get_fpscr() >> 8) & 1)
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int test9(long arg)
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{
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long i;
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int ires;
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unsigned int ures;
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long lres;
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unsigned long ulres;
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unsigned char inv[4];
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struct cvtivals *vp = cvtivals;
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for (i = 0; i < sizeof(cvtivals) / sizeof(cvtivals[0]); ++i, ++vp) {
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set_fpscr(FPS_RN_NEAR);
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asm("lfd 3,0(%0); fctid 4,3; stfd 4,0(%1)"
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: : "b" (&vp->dval), "b" (&lres) : "memory");
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inv[0] = GET_VXCVI();
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set_fpscr(FPS_RN_NEAR);
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asm("fctidu 5,3; stfd 5,0(%0)" : : "b" (&ulres) : "memory");
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inv[1] = GET_VXCVI();
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set_fpscr(FPS_RN_NEAR);
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asm("fctiw 6,3; stfiwx 6,0,%0" : : "b" (&ires) : "memory");
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inv[2] = GET_VXCVI();
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set_fpscr(FPS_RN_NEAR);
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asm("fctiwu 7,3; stfiwx 7,0,%0" : : "b" (&ures) : "memory");
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inv[3] = GET_VXCVI();
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if (lres != vp->lval || ulres != vp->ulval || ires != vp->ival || ures != vp->uival ||
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inv[0] != vp->invalids[0] || inv[1] != vp->invalids[1] ||
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inv[2] != vp->invalids[2] || inv[3] != vp->invalids[3]) {
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print_hex(lres, 16, inv[0]? "V ": " ");
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print_hex(ulres, 16, inv[1]? "V ": " ");
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print_hex(ires, 8, inv[2]? "V ": " ");
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print_hex(ures, 8, inv[3]? "V ": " ");
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return i + 1;
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}
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}
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return 0;
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}
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int fpu_test_9(void)
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{
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enable_fp();
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return trapit(0, test9);
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}
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struct cvtivals cvtizvals[] = {
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{ 0x0000000000000000, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x8000000000000000, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x3fdfffffffffffff, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x3ff0000000000000, 1, 1, 1, 1, {0, 0, 0, 0} },
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{ 0xbff0000000000000, -1, 0, -1, 0, {0, 1, 0, 1} },
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{ 0x402123456789abcd, 8, 8, 8, 8, {0, 0, 0, 0} },
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{ 0x406123456789abcd, 137, 137, 137, 137, {0, 0, 0, 0} },
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{ 0x409123456789abcd, 1096, 1096, 1096, 1096, {0, 0, 0, 0} },
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{ 0x41c123456789abcd, 0x22468acf, 0x22468acf, 0x22468acf, 0x22468acf, {0, 0, 0, 0} },
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{ 0x41d123456789abcd, 0x448d159e, 0x448d159e, 0x448d159e, 0x448d159e, {0, 0, 0, 0} },
|
||||
{ 0x41e123456789abcd, 0x891a2b3c, 0x891a2b3c, 0x7fffffff, 0x891a2b3c, {0, 0, 1, 0} },
|
||||
{ 0x41f123456789abcd, 0x112345678, 0x112345678, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
|
||||
{ 0xc1f123456789abcd, -0x112345678, 0, 0x80000000, 0, {0, 1, 1, 1} },
|
||||
{ 0x432123456789abcd, 0x891a2b3c4d5e6, 0x891a2b3c4d5e6, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
|
||||
{ 0x433123456789abcd, 0x1123456789abcd, 0x1123456789abcd, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
|
||||
{ 0x434123456789abcd, 0x22468acf13579a, 0x22468acf13579a, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
|
||||
{ 0x43c123456789abcd, 0x22468acf13579a00, 0x22468acf13579a00, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
|
||||
{ 0x43d123456789abcd, 0x448d159e26af3400, 0x448d159e26af3400, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
|
||||
{ 0x43e123456789abcd, 0x7fffffffffffffff, 0x891a2b3c4d5e6800, 0x7fffffff, 0xffffffff, {1, 0, 1, 1} },
|
||||
{ 0x43f123456789abcd, 0x7fffffffffffffff, 0xffffffffffffffff, 0x7fffffff, 0xffffffff, {1, 1, 1, 1} },
|
||||
{ 0xc3f123456789abcd, 0x8000000000000000, 0, 0x80000000, 0, {1, 1, 1, 1} },
|
||||
{ 0x7ff0000000000000, 0x7fffffffffffffff, 0xffffffffffffffff, 0x7fffffff, 0xffffffff, {1, 1, 1, 1} },
|
||||
{ 0xfff0000000000000, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
|
||||
{ 0x7ff923456789abcd, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
|
||||
{ 0xfff923456789abcd, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
|
||||
};
|
||||
|
||||
int test10(long arg)
|
||||
{
|
||||
long i;
|
||||
int ires;
|
||||
unsigned int ures;
|
||||
long lres;
|
||||
unsigned long ulres;
|
||||
unsigned char inv[4];
|
||||
struct cvtivals *vp = cvtizvals;
|
||||
|
||||
for (i = 0; i < sizeof(cvtizvals) / sizeof(cvtizvals[0]); ++i, ++vp) {
|
||||
set_fpscr(FPS_RN_NEAR);
|
||||
asm("lfd 3,0(%0); fctidz 4,3; stfd 4,0(%1)"
|
||||
: : "b" (&vp->dval), "b" (&lres) : "memory");
|
||||
inv[0] = GET_VXCVI();
|
||||
set_fpscr(FPS_RN_NEAR);
|
||||
asm("fctiduz 5,3; stfd 5,0(%0)" : : "b" (&ulres) : "memory");
|
||||
inv[1] = GET_VXCVI();
|
||||
set_fpscr(FPS_RN_NEAR);
|
||||
asm("fctiwz 6,3; stfiwx 6,0,%0" : : "b" (&ires) : "memory");
|
||||
inv[2] = GET_VXCVI();
|
||||
set_fpscr(FPS_RN_NEAR);
|
||||
asm("fctiwuz 7,3; stfiwx 7,0,%0" : : "b" (&ures) : "memory");
|
||||
inv[3] = GET_VXCVI();
|
||||
|
||||
if (lres != vp->lval || ulres != vp->ulval || ires != vp->ival || ures != vp->uival ||
|
||||
inv[0] != vp->invalids[0] || inv[1] != vp->invalids[1] ||
|
||||
inv[2] != vp->invalids[2] || inv[3] != vp->invalids[3]) {
|
||||
print_hex(lres, 16, inv[0]? "V ": " ");
|
||||
print_hex(ulres, 16, inv[1]? "V ": " ");
|
||||
print_hex(ires, 8, inv[2]? "V ": " ");
|
||||
print_hex(ures, 8, inv[3]? "V ": " ");
|
||||
return i + 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fpu_test_10(void)
|
||||
{
|
||||
enable_fp();
|
||||
return trapit(0, test10);
|
||||
}
|
||||
|
||||
int fail = 0;
|
||||
|
||||
void do_test(int num, int (*test)(void))
|
||||
@@ -631,6 +786,8 @@ int main(void)
|
||||
do_test(6, fpu_test_6);
|
||||
do_test(7, fpu_test_7);
|
||||
do_test(8, fpu_test_8);
|
||||
do_test(9, fpu_test_9);
|
||||
do_test(10, fpu_test_10);
|
||||
|
||||
return fail;
|
||||
}
|
||||
|
||||
@@ -6,3 +6,5 @@ test 05:PASS
|
||||
test 06:PASS
|
||||
test 07:PASS
|
||||
test 08:PASS
|
||||
test 09:PASS
|
||||
test 10:PASS
|
||||
|
||||
Reference in New Issue
Block a user