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https://github.com/antonblanchard/microwatt.git
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FPU: Implement floating convert to integer instructions
This implements fctiw, fctiwz, fctiwu, fctiwuz, fctid, fctidz, fctidu and fctiduz, and adds tests for them. There are some subtleties around the setting of the inexact (XX) and invalid conversion (VXCVI) flags in the FPSCR. If the rounded value ends up being out of range, we need to set VXCVI and not XX. For a conversion to unsigned word or doubleword of a negative value that rounds to zero, we need to set XX and not VXCVI. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
157
tests/fpu/fpu.c
157
tests/fpu/fpu.c
@@ -19,6 +19,7 @@
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#define FPS_UE 0x20
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#define FPS_OE 0x40
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#define FPS_VE 0x80
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#define FPS_VXCVI 0x100
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#define FPS_VXSOFT 0x400
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extern int trapit(long arg, int (*func)(long));
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@@ -598,6 +599,160 @@ int fpu_test_8(void)
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return trapit(0, test8);
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}
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struct cvtivals {
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unsigned long dval;
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long lval;
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unsigned long ulval;
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int ival;
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unsigned int uival;
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unsigned char invalids[4];
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} cvtivals[] = {
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{ 0x0000000000000000, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x8000000000000000, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x3fdfffffffffffff, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x3ff0000000000000, 1, 1, 1, 1, {0, 0, 0, 0} },
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{ 0xbff0000000000000, -1, 0, -1, 0, {0, 1, 0, 1} },
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{ 0x402123456789abcd, 9, 9, 9, 9, {0, 0, 0, 0} },
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{ 0x406123456789abcd, 137, 137, 137, 137, {0, 0, 0, 0} },
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{ 0x409123456789abcd, 1097, 1097, 1097, 1097, {0, 0, 0, 0} },
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{ 0x41c123456789abcd, 0x22468acf, 0x22468acf, 0x22468acf, 0x22468acf, {0, 0, 0, 0} },
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{ 0x41d123456789abcd, 0x448d159e, 0x448d159e, 0x448d159e, 0x448d159e, {0, 0, 0, 0} },
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{ 0x41e123456789abcd, 0x891a2b3c, 0x891a2b3c, 0x7fffffff, 0x891a2b3c, {0, 0, 1, 0} },
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{ 0x41f123456789abcd, 0x112345679, 0x112345679, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0xc1f123456789abcd, -0x112345679, 0, 0x80000000, 0, {0, 1, 1, 1} },
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{ 0x432123456789abcd, 0x891a2b3c4d5e6, 0x891a2b3c4d5e6, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x433123456789abcd, 0x1123456789abcd, 0x1123456789abcd, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x434123456789abcd, 0x22468acf13579a, 0x22468acf13579a, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x43c123456789abcd, 0x22468acf13579a00, 0x22468acf13579a00, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x43d123456789abcd, 0x448d159e26af3400, 0x448d159e26af3400, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x43e123456789abcd, 0x7fffffffffffffff, 0x891a2b3c4d5e6800, 0x7fffffff, 0xffffffff, {1, 0, 1, 1} },
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{ 0x43f123456789abcd, 0x7fffffffffffffff, 0xffffffffffffffff, 0x7fffffff, 0xffffffff, {1, 1, 1, 1} },
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{ 0xc3f123456789abcd, 0x8000000000000000, 0, 0x80000000, 0, {1, 1, 1, 1} },
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{ 0x7ff0000000000000, 0x7fffffffffffffff, 0xffffffffffffffff, 0x7fffffff, 0xffffffff, {1, 1, 1, 1} },
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{ 0xfff0000000000000, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
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{ 0x7ff923456789abcd, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
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{ 0xfff923456789abcd, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
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{ 0xbfd123456789abcd, 0, 0, 0, 0, {0, 0, 0, 0} },
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};
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#define GET_VXCVI() ((get_fpscr() >> 8) & 1)
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int test9(long arg)
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{
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long i;
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int ires;
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unsigned int ures;
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long lres;
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unsigned long ulres;
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unsigned char inv[4];
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struct cvtivals *vp = cvtivals;
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for (i = 0; i < sizeof(cvtivals) / sizeof(cvtivals[0]); ++i, ++vp) {
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set_fpscr(FPS_RN_NEAR);
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asm("lfd 3,0(%0); fctid 4,3; stfd 4,0(%1)"
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: : "b" (&vp->dval), "b" (&lres) : "memory");
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inv[0] = GET_VXCVI();
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set_fpscr(FPS_RN_NEAR);
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asm("fctidu 5,3; stfd 5,0(%0)" : : "b" (&ulres) : "memory");
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inv[1] = GET_VXCVI();
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set_fpscr(FPS_RN_NEAR);
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asm("fctiw 6,3; stfiwx 6,0,%0" : : "b" (&ires) : "memory");
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inv[2] = GET_VXCVI();
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set_fpscr(FPS_RN_NEAR);
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asm("fctiwu 7,3; stfiwx 7,0,%0" : : "b" (&ures) : "memory");
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inv[3] = GET_VXCVI();
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if (lres != vp->lval || ulres != vp->ulval || ires != vp->ival || ures != vp->uival ||
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inv[0] != vp->invalids[0] || inv[1] != vp->invalids[1] ||
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inv[2] != vp->invalids[2] || inv[3] != vp->invalids[3]) {
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print_hex(lres, 16, inv[0]? "V ": " ");
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print_hex(ulres, 16, inv[1]? "V ": " ");
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print_hex(ires, 8, inv[2]? "V ": " ");
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print_hex(ures, 8, inv[3]? "V ": " ");
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return i + 1;
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}
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}
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return 0;
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}
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int fpu_test_9(void)
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{
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enable_fp();
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return trapit(0, test9);
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}
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struct cvtivals cvtizvals[] = {
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{ 0x0000000000000000, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x8000000000000000, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x3fdfffffffffffff, 0, 0, 0, 0, {0, 0, 0, 0} },
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{ 0x3ff0000000000000, 1, 1, 1, 1, {0, 0, 0, 0} },
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{ 0xbff0000000000000, -1, 0, -1, 0, {0, 1, 0, 1} },
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{ 0x402123456789abcd, 8, 8, 8, 8, {0, 0, 0, 0} },
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{ 0x406123456789abcd, 137, 137, 137, 137, {0, 0, 0, 0} },
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{ 0x409123456789abcd, 1096, 1096, 1096, 1096, {0, 0, 0, 0} },
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{ 0x41c123456789abcd, 0x22468acf, 0x22468acf, 0x22468acf, 0x22468acf, {0, 0, 0, 0} },
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{ 0x41d123456789abcd, 0x448d159e, 0x448d159e, 0x448d159e, 0x448d159e, {0, 0, 0, 0} },
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{ 0x41e123456789abcd, 0x891a2b3c, 0x891a2b3c, 0x7fffffff, 0x891a2b3c, {0, 0, 1, 0} },
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{ 0x41f123456789abcd, 0x112345678, 0x112345678, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0xc1f123456789abcd, -0x112345678, 0, 0x80000000, 0, {0, 1, 1, 1} },
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{ 0x432123456789abcd, 0x891a2b3c4d5e6, 0x891a2b3c4d5e6, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x433123456789abcd, 0x1123456789abcd, 0x1123456789abcd, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x434123456789abcd, 0x22468acf13579a, 0x22468acf13579a, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x43c123456789abcd, 0x22468acf13579a00, 0x22468acf13579a00, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x43d123456789abcd, 0x448d159e26af3400, 0x448d159e26af3400, 0x7fffffff, 0xffffffff, {0, 0, 1, 1} },
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{ 0x43e123456789abcd, 0x7fffffffffffffff, 0x891a2b3c4d5e6800, 0x7fffffff, 0xffffffff, {1, 0, 1, 1} },
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{ 0x43f123456789abcd, 0x7fffffffffffffff, 0xffffffffffffffff, 0x7fffffff, 0xffffffff, {1, 1, 1, 1} },
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{ 0xc3f123456789abcd, 0x8000000000000000, 0, 0x80000000, 0, {1, 1, 1, 1} },
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{ 0x7ff0000000000000, 0x7fffffffffffffff, 0xffffffffffffffff, 0x7fffffff, 0xffffffff, {1, 1, 1, 1} },
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{ 0xfff0000000000000, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
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{ 0x7ff923456789abcd, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
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{ 0xfff923456789abcd, 0x8000000000000000, 0, 0x80000000, 0, { 1, 1, 1, 1 } },
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};
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int test10(long arg)
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{
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long i;
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int ires;
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unsigned int ures;
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long lres;
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unsigned long ulres;
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unsigned char inv[4];
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struct cvtivals *vp = cvtizvals;
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for (i = 0; i < sizeof(cvtizvals) / sizeof(cvtizvals[0]); ++i, ++vp) {
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set_fpscr(FPS_RN_NEAR);
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asm("lfd 3,0(%0); fctidz 4,3; stfd 4,0(%1)"
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: : "b" (&vp->dval), "b" (&lres) : "memory");
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inv[0] = GET_VXCVI();
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set_fpscr(FPS_RN_NEAR);
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asm("fctiduz 5,3; stfd 5,0(%0)" : : "b" (&ulres) : "memory");
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inv[1] = GET_VXCVI();
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set_fpscr(FPS_RN_NEAR);
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asm("fctiwz 6,3; stfiwx 6,0,%0" : : "b" (&ires) : "memory");
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inv[2] = GET_VXCVI();
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set_fpscr(FPS_RN_NEAR);
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asm("fctiwuz 7,3; stfiwx 7,0,%0" : : "b" (&ures) : "memory");
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inv[3] = GET_VXCVI();
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if (lres != vp->lval || ulres != vp->ulval || ires != vp->ival || ures != vp->uival ||
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inv[0] != vp->invalids[0] || inv[1] != vp->invalids[1] ||
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inv[2] != vp->invalids[2] || inv[3] != vp->invalids[3]) {
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print_hex(lres, 16, inv[0]? "V ": " ");
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print_hex(ulres, 16, inv[1]? "V ": " ");
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print_hex(ires, 8, inv[2]? "V ": " ");
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print_hex(ures, 8, inv[3]? "V ": " ");
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return i + 1;
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}
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}
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return 0;
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}
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int fpu_test_10(void)
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{
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enable_fp();
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return trapit(0, test10);
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}
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int fail = 0;
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void do_test(int num, int (*test)(void))
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@@ -631,6 +786,8 @@ int main(void)
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do_test(6, fpu_test_6);
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do_test(7, fpu_test_7);
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do_test(8, fpu_test_8);
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do_test(9, fpu_test_9);
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do_test(10, fpu_test_10);
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return fail;
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}
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