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FPU: Set sign of 0 result of subtraction in pack_dp
When a floating-point subtraction results in a zero result, the sign of the result is required to be positive in all rounding modes except the round to minus infinity mode, when it is negative. Consolidate the logic for doing this in one place, in the pack_dp function, instead of having it at each place where a zero result is generated. Since fnmadd[s] and fnmsub[s] negate the result after this rule has been applied, we use the r.negate signal to indicate a negation which is now done in pack_dp. Thus the EXC_RESULT state no longer uses r.negate, and in fact doesn't set v.result_sign at all; that is now done in the states that lead into EXC_RESULT. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
parent
932da4c114
commit
09965b9102
73
fpu.vhdl
73
fpu.vhdl
@ -169,6 +169,9 @@ architecture behaviour of fpu is
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oe : std_ulogic;
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xerc : xer_common_t;
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xerc_result : xer_common_t;
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res_negate : std_ulogic;
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res_subtract : std_ulogic;
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res_rmode : std_ulogic_vector(2 downto 0);
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end record;
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type lookup_table is array(0 to 1023) of std_ulogic_vector(17 downto 0);
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@ -605,15 +608,21 @@ architecture behaviour of fpu is
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end;
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-- Construct a DP floating-point result from components
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function pack_dp(sign: std_ulogic; class: fp_number_class; exp: signed(EXP_BITS-1 downto 0);
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mantissa: std_ulogic_vector; single_prec: std_ulogic; quieten_nan: std_ulogic)
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function pack_dp(negative: std_ulogic; class: fp_number_class; exp: signed(EXP_BITS-1 downto 0);
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mantissa: std_ulogic_vector; single_prec: std_ulogic; quieten_nan: std_ulogic;
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negate: std_ulogic; is_subtract: std_ulogic; round_mode: std_ulogic_vector)
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return std_ulogic_vector is
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variable dp_result : std_ulogic_vector(63 downto 0);
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variable sign : std_ulogic;
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begin
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dp_result := (others => '0');
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dp_result(63) := sign;
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sign := negative;
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case class is
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when ZERO =>
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if is_subtract = '1' then
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-- set result sign depending on rounding mode
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sign := round_mode(0) and round_mode(1);
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end if;
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when FINITE =>
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if mantissa(UNIT_BIT) = '1' then
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-- normalized number
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@ -633,6 +642,7 @@ architecture behaviour of fpu is
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dp_result(28 downto 0) := mantissa(SP_LSB - 1 downto DP_LSB);
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end if;
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end case;
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dp_result(63) := sign xor negate;
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return dp_result;
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end;
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@ -1468,8 +1478,8 @@ begin
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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is_add := r.a.negative xor r.b.negative xor r.insn(1);
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v.is_subtract := not is_add;
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if r.a.class = FINITE and r.b.class = FINITE then
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v.is_subtract := not is_add;
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v.add_bsmall := r.exp_cmp;
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v.opsel_a := AIN_B;
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if r.exp_cmp = '0' then
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@ -1491,18 +1501,13 @@ begin
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v.fpscr(FPSCR_VXISI) := '1';
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qnan_result := '1';
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arith_done := '1';
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elsif r.a.class = ZERO and r.b.class = ZERO and is_add = '0' then
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-- return -0 for rounding to -infinity
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v.result_sign := r.round_mode(1) and r.round_mode(0);
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arith_done := '1';
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elsif r.a.class = INFINITY or r.b.class = ZERO then
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-- result is A
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v.opsel_a := AIN_A;
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v.state := EXC_RESULT;
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-- result is A; we're already set up to put A into R
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arith_done := '1';
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else
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-- result is +/- B
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v.opsel_a := AIN_B;
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v.negate := not r.insn(1);
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v.result_sign := r.b.negative xnor r.insn(1);
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v.state := EXC_RESULT;
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end if;
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end if;
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@ -1541,7 +1546,6 @@ begin
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else
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-- r.c.class is ZERO or INFINITY
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v.opsel_a := AIN_C;
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v.negate := r.a.negative;
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v.state := EXC_RESULT;
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end if;
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end if;
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@ -1599,8 +1603,10 @@ begin
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v.fpscr(FPSCR_FI) := '0';
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if r.a.class = ZERO or (r.a.negative = '0' and r.a.class /= NAN) then
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v.opsel_a := AIN_C;
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v.result_sign := r.c.negative;
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else
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v.opsel_a := AIN_B;
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v.result_sign := r.b.negative;
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end if;
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v.quieten_nan := '0';
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v.state := EXC_RESULT;
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@ -1720,9 +1726,10 @@ begin
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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is_add := r.a.negative xor r.c.negative xor r.b.negative xor r.insn(1);
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v.negate := r.insn(2);
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v.is_subtract := not is_add;
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if r.a.class = FINITE and r.c.class = FINITE and
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(r.b.class = FINITE or r.b.class = ZERO) then
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v.is_subtract := not is_add;
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-- Make sure A and C are normalized
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if r.a.mantissa(UNIT_BIT) = '0' then
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v.state := RENORM_A;
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@ -1730,13 +1737,13 @@ begin
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v.state := RENORM_C;
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elsif r.b.class = ZERO then
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-- no addend, degenerates to multiply
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v.result_sign := r.a.negative xor r.c.negative xor r.insn(2);
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v.result_sign := r.a.negative xor r.c.negative;
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f_to_multiply.valid <= '1';
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v.is_multiply := '1';
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v.state := MULT_1;
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elsif r.madd_cmp = '0' then
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-- addend is bigger, do multiply first
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v.result_sign := not (r.b.negative xor r.insn(1) xor r.insn(2));
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v.result_sign := r.b.negative xnor r.insn(1);
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f_to_multiply.valid <= '1';
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v.first := '1';
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v.state := FMADD_0;
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@ -1760,19 +1767,14 @@ begin
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else
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-- result is infinity
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v.result_class := INFINITY;
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v.result_sign := r.a.negative xor r.c.negative xor r.insn(2);
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v.result_sign := r.a.negative xor r.c.negative;
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arith_done := '1';
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end if;
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else
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-- Here A is zero, C is zero, or B is infinity
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-- Result is +/-B in all of those cases
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v.opsel_a := AIN_B;
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if r.b.class /= ZERO or is_add = '1' then
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v.negate := not (r.insn(1) xor r.insn(2));
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else
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-- have to be careful about rule for 0 - 0 result sign
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v.negate := r.b.negative xor (r.round_mode(1) and r.round_mode(0)) xor r.insn(2);
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end if;
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v.result_sign := r.b.negative xnor r.insn(1);
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v.state := EXC_RESULT;
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end if;
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end if;
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@ -1910,10 +1912,6 @@ begin
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elsif (r_hi_nz or r_lo_nz or (or (r.r(DP_LSB - 1 downto 0)))) = '0' then
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-- r.x must be zero at this point
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v.result_class := ZERO;
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if r.is_subtract = '1' then
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-- set result sign depending on rounding mode
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v.result_sign := r.round_mode(1) and r.round_mode(0);
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end if;
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arith_done := '1';
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else
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rs_norm <= '1';
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@ -1970,7 +1968,7 @@ begin
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-- product is bigger here
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-- shift B right and use it as the addend to the multiplier
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-- for subtract, multiplier does B - A * C
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v.result_sign := r.a.negative xor r.c.negative xor r.insn(2) xor r.is_subtract;
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v.result_sign := r.a.negative xor r.c.negative xor r.is_subtract;
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re_sel2 <= REXP2_B;
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re_set_result <= '1';
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-- set shift to b.exp - result_exp + 64
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@ -2030,7 +2028,6 @@ begin
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if s_nz = '0' then
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-- must be a subtraction, and r.x must be zero
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v.result_class := ZERO;
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v.result_sign := r.round_mode(1) and r.round_mode(0);
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arith_done := '1';
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else
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-- R is all zeroes but there are non-zero bits in S
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@ -2572,10 +2569,6 @@ begin
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rs_neg2 <= '1';
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if mant_nz = '0' then
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v.result_class := ZERO;
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if r.is_subtract = '1' then
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-- set result sign depending on rounding mode
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v.result_sign := r.round_mode(1) and r.round_mode(0);
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end if;
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arith_done := '1';
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else
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-- Renormalize result after rounding
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@ -2597,6 +2590,7 @@ begin
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arith_done := '1';
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when NAN_RESULT =>
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v.negate := '0';
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if (r.use_a = '1' and r.a.class = NAN and r.a.mantissa(QNAN_BIT) = '0') or
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(r.use_b = '1' and r.b.class = NAN and r.b.mantissa(QNAN_BIT) = '0') or
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(r.use_c = '1' and r.c.class = NAN and r.c.mantissa(QNAN_BIT) = '0') then
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@ -2606,10 +2600,13 @@ begin
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end if;
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if r.use_a = '1' and r.a.class = NAN then
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v.opsel_a := AIN_A;
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v.result_sign := r.a.negative;
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elsif r.use_b = '1' and r.b.class = NAN then
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v.opsel_a := AIN_B;
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v.result_sign := r.b.negative;
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elsif r.use_c = '1' and r.c.class = NAN then
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v.opsel_a := AIN_C;
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v.result_sign := r.c.negative;
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end if;
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v.state := EXC_RESULT;
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@ -2617,15 +2614,12 @@ begin
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-- r.opsel_a = AIN_A, AIN_B or AIN_C according to which input is the result
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case r.opsel_a is
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when AIN_B =>
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v.result_sign := r.b.negative xor r.negate;
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re_sel2 <= REXP2_B;
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v.result_class := r.b.class;
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when AIN_C =>
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v.result_sign := r.c.negative xor r.negate;
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re_sel2 <= REXP2_C;
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v.result_class := r.c.class;
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when others =>
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v.result_sign := r.a.negative xor r.negate;
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re_sel1 <= REXP1_A;
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v.result_class := r.a.class;
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end case;
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@ -3171,6 +3165,7 @@ begin
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invalid := '1';
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v.result_class := NAN;
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v.result_sign := '0';
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v.negate := '0';
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misc_sel <= "0001";
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opsel_r <= RES_MISC;
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arith_done := '1';
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@ -3550,6 +3545,9 @@ begin
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v.int_result := int_result;
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v.illegal := illegal;
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v.nsnan_result := v.quieten_nan;
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v.res_negate := v.negate;
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v.res_subtract := v.is_subtract;
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v.res_rmode := r.round_mode;
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if r.integer_op = '1' then
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v.cr_mask := num_to_fxm(0);
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elsif r.is_cmp = '0' then
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@ -3581,7 +3579,8 @@ begin
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fp_result <= r.r;
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else
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fp_result <= pack_dp(r.result_sign, r.result_class, r.result_exp, r.r,
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r.sp_result, r.nsnan_result);
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r.sp_result, r.nsnan_result,
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r.res_negate, r.res_subtract, r.res_rmode);
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end if;
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rin <= v;
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