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Fix a Diamond build issue in writeback

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Diamond doesn't like the "" & method of converting std_logic to a single bit
std_logic_vector. Thanks to Olof Kindgren for this patch.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2020-01-23 11:37:24 +11:00
committed by Anton Blanchard
parent 39596dc70a
commit 0de83edf2e
1 changed files with 6 additions and 6 deletions
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12
writeback.vhdl
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@@ -64,16 +64,16 @@ begin
variable zero : std_ulogic;
variable sign : std_ulogic;
begin
x := "" & e_in.valid;
y := "" & l_in.valid;
x(0) := e_in.valid;
y(0) := l_in.valid;
assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
x := "" & e_in.write_enable;
y := "" & l_in.write_enable;
x(0) := e_in.write_enable;
y(0) := l_in.write_enable;
assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
w := "" & e_in.write_cr_enable;
x := "" & (e_in.write_enable and e_in.rc);
w(0) := e_in.write_cr_enable;
x(0) := (e_in.write_enable and e_in.rc);
assert (to_integer(unsigned(w)) + to_integer(unsigned(x))) <= 1 severity failure;
w_out <= WritebackToRegisterFileInit;