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liteeth: Update yaml config

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csr_data_width is no longer required. Add ntxslots and nrxslots
parameters but set them to the default value.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2021-08-09 13:49:25 +10:00
committed by Anton Blanchard
parent 458dfe01a6
commit 12efb51bcc
2 changed files with 4 additions and 2 deletions
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3
liteeth/gen-src/arty.yml
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@@ -8,8 +8,9 @@ vendor: xilinx
clk_freq: 100e6
core: wishbone
endianness: little
ntxslots: 2
nrxslots: 2
soc:
mem_map:
ethmac: 0x00010000
csr_data_width: 32

3
liteeth/gen-src/nexys-video.yml
View File

@@ -8,8 +8,9 @@ vendor: xilinx
clk_freq: 125e6
core: wishbone
endianness: little
ntxslots: 2
nrxslots: 2
soc:
mem_map:
ethmac: 0x00010000
csr_data_width: 32