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Merge pull request #314 from antonblanchard/yosys-go-fast-bits

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Reduce Yosys ECP5 cell usage by 30% with -abc9 -nowidelut
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Paul Mackerras
2021-08-11 16:26:29 +10:00
committed by GitHub
parent 400e481ffa 6254bb5ee9
commit 1896e5f803
1 changed files with 1 additions and 1 deletions
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Makefile
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@@ -196,7 +196,7 @@ fpga_files = fpga/soc_reset.vhdl \
synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
microwatt.json: $(synth_files) $(RAM_INIT_FILE)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -abc9 -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files)
microwatt.v: $(synth_files) $(RAM_INIT_FILE)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"