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genesys2: Fix SPI_FLASH_OFFSET (#449)

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Signed-off-by: Boris Shingarov <shingarov@labware.com>
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Boris Shingarov 2025-08-17 19:48:23 -04:00 committed by GitHub
parent a6858f716a
commit 198ad6d199
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GPG Key ID: B5690EEEBB952194
2 changed files with 3 additions and 3 deletions
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2
fpga/top-genesys2.vhdl
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@ -17,7 +17,7 @@ entity toplevel is
USE_LITEDRAM : boolean := false;
NO_BRAM : boolean := false;
DISABLE_FLATTEN_CORE : boolean := false;
SPI_FLASH_OFFSET : integer := 10485760;
SPI_FLASH_OFFSET : integer := 12582912;
SPI_FLASH_DEF_CKDV : natural := 1;
SPI_FLASH_DEF_QUAD : boolean := true;
LOG_LENGTH : natural := 2048;

4
microwatt.core
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@ -185,7 +185,7 @@ targets:
- use_litedram=false
- no_bram=false
- disable_flatten_core
- spi_flash_offset=10485760
- spi_flash_offset=12582912
- log_length=2048
- uart_is_16550=false
generate: [git_hash]
@ -222,7 +222,7 @@ targets:
- use_litedram=true
- disable_flatten_core
- no_bram
- spi_flash_offset=10485760
- spi_flash_offset=12582912
- log_length=2048
- uart_is_16550=false
generate: [litedram_genesys2, git_hash]