core: Implement LPCR register

This implements the LPCR (Logical Partition Control Register) with 5
read/write bits.  The other 59 bits are read-only; two (HR and UPRT)
read as 1 and the rest as 0.

The bits that are implemented are:
* HAIL - enables taking interrupts with relocation on
* LD - enables large decrementer mode
* HEIC - disables external interrupts when set
* LPES - controls how external interrupts are delivered
* HVICE - does nothing at present since there is no source of
  	  Hypervisor Virtualization Interrupts.

This also fixes a bug where MSR[RI] was getting cleared by the
delivery of hypervisor interrupts.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

scripts/mw_debug/mw_debug.c

@@ -552,7 +552,7 @@ static const char *fast_spr_names[] =
 	"lr", "ctr", "srr0", "srr1", "hsrr0", "hsrr1",
 	"sprg0", "sprg1", "sprg2", "sprg3",
 	"hsprg0", "hsprg1", "xer", "tar",
-	"fscr", "unused", "heir", "cfar",
+	"fscr", "lpcr", "heir", "cfar",
 };
 
 static const char *ldst_spr_names[] = {