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Merge pull request #31 from antonblanchard/no-second-write-port-2

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More second write port removal
This commit is contained in:
Anton Blanchard
2019-09-09 16:12:59 +10:00
committed by GitHub
parent 045a00c5d7 31a6fb6ef5
commit 2241b71674
2 changed files with 1 additions and 9 deletions
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5
common.vhdl
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@@ -170,11 +170,8 @@ package common is
write_reg : std_ulogic_vector(4 downto 0);
write_data : std_ulogic_vector(63 downto 0);
write_enable : std_ulogic;
write_reg2 : std_ulogic_vector(4 downto 0);
write_data2 : std_ulogic_vector(63 downto 0);
write_enable2 : std_ulogic;
end record;
constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_enable2 => '0', others => (others => '0'));
constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
type WritebackToCrFileType is record
write_cr_enable : std_ulogic;

5
register_file.vhdl
View File

@@ -31,11 +31,6 @@ begin
report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
end if;
if w_in.write_enable2 = '1' then
assert not(is_x(w_in.write_data2)) and not(is_x(w_in.write_reg2)) severity failure;
report "Writing GPR " & to_hstring(w_in.write_reg2) & " " & to_hstring(w_in.write_data2);
registers(to_integer(unsigned(w_in.write_reg2))) <= w_in.write_data2;
end if;
end if;
end process register_write_0;