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https://github.com/antonblanchard/microwatt.git
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Rework Makefile
Instead of building each file one by one (and having to track all the dependencies manually), use the ghdl -c command that does analysis and elaboration in one go. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
committed by
Anton Blanchard
Anton Blanchard
parent
b82d07c8d5
commit
224e7734a8
148
Makefile
148
Makefile
@@ -1,134 +1,62 @@
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GHDL=ghdl
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GHDLFLAGS=--std=08 -Psim-unisim
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GHDLFLAGS=--std=08 --work=unisim
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CFLAGS=-O2 -Wall
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# We need a version of GHDL built with either the LLVM or gcc backend.
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# Fedora provides this, but other distros may not. Another option, although
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# rather slow, is to use the Docker image.
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# Fedora provides this, but other distros may not. Another option is to use
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# the Docker image.
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#
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# Uncomment one of these to build with Docker or podman
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#DOCKER=docker
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#DOCKER=podman
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DOCKER=podman
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#
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# Uncomment these lines to build with Docker/podman
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#PWD = $(shell pwd)
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#DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
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#GHDL = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
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#CC = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
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PWD = $(shell pwd)
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DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
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GHDL = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
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CC = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
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all = core_tb soc_reset_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
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rotator_tb countzero_tb wishbone_bram_tb
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# XXX
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# loadstore_tb fetch_tb
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all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
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rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
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all: $(all)
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%.o : %.vhdl
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$(GHDL) -a $(GHDLFLAGS) --workdir=$(shell dirname $@) $<
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CORE_FILES=decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl
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CORE_FILES+=fetch2.vhdl utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl
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CORE_FILES+=decode1.vhdl helpers.vhdl insn_helpers.vhdl gpr_hazard.vhdl
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CORE_FILES+=cr_hazard.vhdl control.vhdl decode2.vhdl register_file.vhdl
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CORE_FILES+=cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl
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CORE_FILES+=logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl
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CORE_FILES+=execute1.vhdl loadstore1.vhdl mmu.vhdl dcache.vhdl
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CORE_FILES+=writeback.vhdl core_debug.vhdl core.vhdl
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common.o: decode_types.o
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control.o: gpr_hazard.o cr_hazard.o common.o
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sim_jtag.o: sim_jtag_socket.o
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core_tb.o: common.o wishbone_types.o core.o soc.o sim_jtag.o
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core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o loadstore1.o mmu.o dcache.o writeback.o core_debug.o
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core_debug.o: common.o
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countzero.o:
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countzero_tb.o: common.o glibc_random.o countzero.o
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cr_file.o: common.o
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crhelpers.o: common.o
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decode1.o: common.o decode_types.o
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decode2.o: decode_types.o common.o helpers.o insn_helpers.o control.o
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decode_types.o:
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execute1.o: decode_types.o common.o helpers.o crhelpers.o insn_helpers.o ppc_fx_insns.o rotator.o logical.o countzero.o multiply.o divider.o
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fetch1.o: common.o
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fetch2.o: common.o wishbone_types.o
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glibc_random_helpers.o:
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glibc_random.o: glibc_random_helpers.o
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helpers.o:
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cache_ram.o:
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plru.o:
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plru_tb.o: plru.o
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utils.o:
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sim_bram.o: sim_bram_helpers.o utils.o
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wishbone_bram_wrapper.o: wishbone_types.o sim_bram.o utils.o
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wishbone_bram_tb.o: wishbone_bram_wrapper.o
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icache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
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icache_tb.o: common.o wishbone_types.o icache.o wishbone_bram_wrapper.o
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dcache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
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dcache_tb.o: common.o wishbone_types.o dcache.o wishbone_bram_wrapper.o
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insn_helpers.o:
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loadstore1.o: common.o decode_types.o
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logical.o: decode_types.o
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multiply_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o multiply.o
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multiply.o: common.o decode_types.o
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mmu.o: common.o
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divider_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o divider.o
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divider.o: common.o decode_types.o
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ppc_fx_insns.o: helpers.o
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register_file.o: common.o
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rotator.o: common.o
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rotator_tb.o: common.o glibc_random.o ppc_fx_insns.o insn_helpers.o rotator.o
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sim_console.o:
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sim_uart.o: wishbone_types.o sim_console.o
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xics.o: wishbone_types.o common.o
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soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o wishbone_bram_wrapper.o dmi_dtm_xilinx.o wishbone_debug_master.o xics.o syscon.o
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syscon.o: wishbone_types.o
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wishbone_arbiter.o: wishbone_types.o
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wishbone_types.o:
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writeback.o: common.o crhelpers.o
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dmi_dtm_tb.o: dmi_dtm_xilinx.o wishbone_debug_master.o
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dmi_dtm_xilinx.o: wishbone_types.o sim-unisim/unisim_vcomponents.o
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wishbone_debug_master.o: wishbone_types.o
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SOC_FILES=wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl
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SOC_FILES+=wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl
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UNISIM_BITS = sim-unisim/unisim_vcomponents.vhdl sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl
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sim-unisim/unisim_vcomponents.o: $(UNISIM_BITS)
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$(GHDL) -a $(GHDLFLAGS) --work=unisim --workdir=sim-unisim $^
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SOC_SIM_FILES=sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl
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SOC_SIM_FILES+=sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl
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SOC_SIM_FILES+=sim-unisim/BUFG.vhdl sim-unisim/unisim_vcomponents.vhdl
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SOC_SIM_FILES+=dmi_dtm_xilinx.vhdl
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SOC_SIM_C_FILES=sim_vhpi_c.o sim_bram_helpers_c.o sim_console_c.o
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SOC_SIM_C_FILES+=sim_jtag_socket_c.o
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SOC_SIM_OBJ_FILES=$(SOC_SIM_C_FILES:.c=.o)
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comma := ,
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SOC_SIM_LINK=$(patsubst %,-Wl$(comma)%,$(SOC_SIM_OBJ_FILES))
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fpga/soc_reset_tb.o: fpga/soc_reset.o
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CORE_TBS=multiply_tb divider_tb rotator_tb countzero_tb
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SOC_TBS=core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
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soc_reset_tb: fpga/soc_reset_tb.o fpga/soc_reset.o
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$(GHDL) -e $(GHDLFLAGS) --workdir=fpga soc_reset_tb
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$(processes): %_processes: tests/%.o main.c
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core_tb: core_tb.o sim_vhpi_c.o sim_bram_helpers_c.o sim_console_c.o sim_jtag_socket_c.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o $@
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$(SOC_TBS): %: $(CORE_FILES) $(SOC_FILES) $(SOC_SIM_FILES) $(SOC_SIM_OBJ_FILES) %.vhdl
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$(GHDL) -c $(GHDLFLAGS) $(SOC_SIM_LINK) $(CORE_FILES) $(SOC_FILES) $(SOC_SIM_FILES) $@.vhdl -e $@
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fetch_tb: fetch_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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$(CORE_TBS): %: $(CORE_FILES) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
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$(GHDL) -c $(GHDLFLAGS) $(CORE_FILES) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@
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icache_tb: icache_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
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dcache_tb: dcache_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
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plru_tb: plru_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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loadstore_tb: loadstore_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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multiply_tb: multiply_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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divider_tb: divider_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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rotator_tb: rotator_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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countzero_tb: countzero_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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simple_ram_tb: simple_ram_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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wishbone_bram_tb: sim_vhpi_c.o sim_bram_helpers_c.o wishbone_bram_tb.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
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dmi_dtm_tb: dmi_dtm_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
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soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
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$(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
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tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
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tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
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