mirror of
https://github.com/antonblanchard/microwatt.git
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divider: Do absolute-value ops in divider instead of decode
This moves the negation of negative operands for signed divide and modulus operations out of the decode2 stage and into the divider. If either of the operands for a signed divide or modulus operation is negative, the divider now takes an extra cycle to negate the operands that are negative. The interface to the divider now has an 'is_signed' signal rather than a 'neg_result' signal, and the dividend and divisor can be negative, so divider_tb had to be updated for the new interface. The reason for doing this is that one of the worst timing violations on the Arty A7-100 at 100MHz involved the carry chain in the adders that did the negation of the dividend and divisor in the decode stage. Moving the negations to a separate cycle fixes that and also seems to reduce the total number of slice LUTs used. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
parent
e6536d4b8b
commit
25b9450475
@ -81,13 +81,13 @@ package common is
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write_reg: std_ulogic_vector(4 downto 0);
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dividend: std_ulogic_vector(63 downto 0);
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divisor: std_ulogic_vector(63 downto 0);
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neg_result: std_ulogic;
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is_signed: std_ulogic;
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is_32bit: std_ulogic;
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is_extended: std_ulogic;
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is_modulus: std_ulogic;
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rc: std_ulogic;
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end record;
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constant Decode2ToDividerInit: Decode2ToDividerType := (valid => '0', neg_result => '0', is_32bit => '0', is_extended => '0', is_modulus => '0', rc => '0', others => (others => '0'));
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constant Decode2ToDividerInit: Decode2ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0', is_extended => '0', is_modulus => '0', rc => '0', others => (others => '0'));
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type Decode2ToRegisterFileType is record
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read1_enable : std_ulogic;
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57
decode2.vhdl
57
decode2.vhdl
@ -221,9 +221,6 @@ begin
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variable v_int : reg_internal_type;
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variable mul_a : std_ulogic_vector(63 downto 0);
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variable mul_b : std_ulogic_vector(63 downto 0);
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variable dividend : std_ulogic_vector(63 downto 0);
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variable divisor : std_ulogic_vector(63 downto 0);
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variable absdend : std_ulogic_vector(31 downto 0);
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variable decoded_reg_a : decode_input_reg_t;
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variable decoded_reg_b : decode_input_reg_t;
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variable decoded_reg_c : decode_input_reg_t;
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@ -308,60 +305,36 @@ begin
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-- s = 1 for signed, 0 for unsigned (for div*)
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-- t = 1 for 32-bit, 0 for 64-bit
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-- r = RC bit (record condition code)
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-- For signed division/modulus, we take absolute values and
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-- tell the divider what the sign of the result should be,
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-- which is the dividend sign for modulus, and the XOR of
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-- the dividend and divisor signs for division.
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dividend := decoded_reg_a.data;
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divisor := decoded_reg_b.data;
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v.d.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
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v.d.is_modulus := not d_in.insn(8);
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v.d.is_32bit := not d_in.insn(2);
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if d_in.insn(8) = '1' then
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signed_division := d_in.insn(6);
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signed_division := d_in.insn(6);
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else
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signed_division := d_in.insn(10);
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signed_division := d_in.insn(10);
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end if;
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v.d.is_signed := signed_division;
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if d_in.insn(2) = '0' then
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-- 64-bit forms
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v.d.is_32bit := '0';
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-- 64-bit forms
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if d_in.insn(8) = '1' and d_in.insn(7) = '0' then
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v.d.is_extended := '1';
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end if;
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if signed_division = '1' and dividend(63) = '1' then
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v.d.neg_result := '1';
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v.d.dividend := std_ulogic_vector(- signed(dividend));
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else
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v.d.dividend := dividend;
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end if;
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if signed_division = '1' and divisor(63) = '1' then
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if d_in.insn(8) = '1' then
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v.d.neg_result := not v.d.neg_result;
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end if;
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v.d.divisor := std_ulogic_vector(- signed(divisor));
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else
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v.d.divisor := divisor;
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end if;
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v.d.dividend := decoded_reg_a.data;
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v.d.divisor := decoded_reg_b.data;
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else
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-- 32-bit forms
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v.d.is_32bit := '1';
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if signed_division = '1' and dividend(31) = '1' then
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v.d.neg_result := '1';
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absdend := std_ulogic_vector(- signed(dividend(31 downto 0)));
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else
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absdend := dividend(31 downto 0);
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end if;
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if d_in.insn(8) = '1' and d_in.insn(7) = '0' then -- extended forms
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v.d.dividend := absdend & x"00000000";
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v.d.dividend := decoded_reg_a.data(31 downto 0) & x"00000000";
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elsif signed_division = '1' and decoded_reg_a.data(31) = '1' then
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-- sign extend to 64 bits
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v.d.dividend := x"ffffffff" & decoded_reg_a.data(31 downto 0);
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else
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v.d.dividend := x"00000000" & absdend;
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v.d.dividend := x"00000000" & decoded_reg_a.data(31 downto 0);
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end if;
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if signed_division = '1' and divisor(31) = '1' then
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if d_in.insn(8) = '1' then
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v.d.neg_result := not v.d.neg_result;
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end if;
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v.d.divisor := x"00000000" & std_ulogic_vector(- signed(divisor(31 downto 0)));
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if signed_division = '1' and decoded_reg_b.data(31) = '1' then
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v.d.divisor := x"ffffffff" & decoded_reg_b.data(31 downto 0);
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else
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v.d.divisor := x"00000000" & divisor(31 downto 0);
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v.d.divisor := x"00000000" & decoded_reg_b.data(31 downto 0);
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end if;
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end if;
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v.d.rc := decode_rc(d_in.decode.rc, d_in.insn);
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21
divider.vhdl
21
divider.vhdl
@ -24,10 +24,12 @@ architecture behaviour of divider is
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signal sresult : std_ulogic_vector(63 downto 0);
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signal qbit : std_ulogic;
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signal running : std_ulogic;
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signal signcheck : std_ulogic;
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signal count : unsigned(6 downto 0);
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signal neg_result : std_ulogic;
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signal is_modulus : std_ulogic;
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signal is_32bit : std_ulogic;
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signal extended : std_ulogic;
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signal rc : std_ulogic;
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signal write_reg : std_ulogic_vector(4 downto 0);
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@ -64,7 +66,7 @@ begin
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running <= '0';
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count <= "0000000";
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elsif d_in.valid = '1' then
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if d_in.is_extended = '1' then
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if d_in.is_extended = '1' and not (d_in.is_signed = '1' and d_in.dividend(63) = '1') then
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dend <= d_in.dividend & x"0000000000000000";
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else
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dend <= x"0000000000000000" & d_in.dividend;
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@ -72,12 +74,27 @@ begin
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div <= unsigned(d_in.divisor);
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quot <= (others => '0');
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write_reg <= d_in.write_reg;
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neg_result <= d_in.neg_result;
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neg_result <= '0';
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is_modulus <= d_in.is_modulus;
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extended <= d_in.is_extended;
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is_32bit <= d_in.is_32bit;
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rc <= d_in.rc;
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count <= "0000000";
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running <= '1';
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signcheck <= d_in.is_signed and (d_in.dividend(63) or d_in.divisor(63));
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elsif signcheck = '1' then
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signcheck <= '0';
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neg_result <= dend(63) xor (div(63) and not is_modulus);
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if dend(63) = '1' then
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if extended = '1' then
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dend <= std_ulogic_vector(- signed(dend(63 downto 0))) & x"0000000000000000";
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else
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dend <= x"0000000000000000" & std_ulogic_vector(- signed(dend(63 downto 0)));
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end if;
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end if;
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if div(63) = '1' then
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div <= unsigned(- signed(div));
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end if;
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elsif running = '1' then
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if count = "0111111" then
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running <= '0';
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174
divider_tb.vhdl
174
divider_tb.vhdl
@ -44,7 +44,7 @@ begin
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d1.write_reg <= "10001";
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d1.dividend <= x"0000000010001000";
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d1.divisor <= x"0000000000001111";
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d1.neg_result <= '0';
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d1.is_signed <= '0';
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d1.is_32bit <= '0';
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d1.is_extended <= '0';
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d1.is_modulus <= '0';
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@ -55,7 +55,7 @@ begin
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d1.valid <= '0';
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for j in 0 to 64 loop
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for j in 0 to 65 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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@ -79,7 +79,7 @@ begin
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d1.valid <= '0';
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for j in 0 to 64 loop
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for j in 0 to 65 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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@ -105,27 +105,15 @@ begin
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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if ra(63) = '1' then
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d1.dividend <= std_ulogic_vector(- signed(ra));
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else
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d1.dividend <= ra;
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end if;
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if rb(63) = '1' then
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d1.divisor <= std_ulogic_vector(- signed(rb));
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else
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d1.divisor <= rb;
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end if;
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if ra(63) = rb(63) then
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d1.neg_result <= '0';
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else
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d1.neg_result <= '1';
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end if;
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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for j in 0 to 65 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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@ -154,13 +142,13 @@ begin
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.neg_result <= '0';
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d1.is_signed <= '0';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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for j in 0 to 65 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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@ -187,28 +175,16 @@ begin
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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if ra(63) = '1' then
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d1.dividend <= std_ulogic_vector(- signed(ra));
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else
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d1.dividend <= ra;
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end if;
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if rb(63) = '1' then
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d1.divisor <= std_ulogic_vector(- signed(rb));
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else
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d1.divisor <= rb;
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end if;
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if ra(63) = rb(63) then
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d1.neg_result <= '0';
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else
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d1.neg_result <= '1';
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end if;
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '1';
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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for j in 0 to 65 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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@ -216,14 +192,17 @@ begin
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end loop;
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assert d2.valid = '1';
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if unsigned(d1.divisor) > unsigned(d1.dividend) then
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if rb /= x"0000000000000000" then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(signed(d128) / signed(rb));
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behave_rt := q128(63 downto 0);
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divde expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divde";
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if q128(127 downto 63) = x"0000000000000000" & '0' or
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q128(127 downto 63) = x"ffffffffffffffff" & '1' then
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behave_rt := q128(63 downto 0);
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divde expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divde";
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end if;
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end if;
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end loop;
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end loop;
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@ -239,14 +218,14 @@ begin
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.neg_result <= '0';
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d1.is_signed <= '0';
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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for j in 0 to 65 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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@ -254,7 +233,7 @@ begin
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end loop;
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assert d2.valid = '1';
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if unsigned(d1.divisor) > unsigned(d1.dividend) then
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if unsigned(rb) > unsigned(ra) then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(unsigned(d128) / unsigned(rb));
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behave_rt := q128(63 downto 0);
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@ -275,21 +254,9 @@ begin
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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if ra(63) = '1' then
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d1.dividend <= std_ulogic_vector(- signed(ra));
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else
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d1.dividend <= ra;
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end if;
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if rb(63) = '1' then
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d1.divisor <= std_ulogic_vector(- signed(rb));
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else
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d1.divisor <= rb;
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end if;
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if ra(63) = rb(63) then
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d1.neg_result <= '0';
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else
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d1.neg_result <= '1';
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end if;
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '1';
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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@ -297,7 +264,7 @@ begin
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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for j in 0 to 65 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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@ -326,7 +293,7 @@ begin
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.neg_result <= '0';
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d1.is_signed <= '0';
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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@ -334,7 +301,7 @@ begin
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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for j in 0 to 65 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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@ -361,21 +328,9 @@ begin
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 32)) & x"00000000";
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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if ra(63) = '1' then
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d1.dividend <= std_ulogic_vector(- signed(ra));
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else
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d1.dividend <= ra;
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end if;
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if rb(63) = '1' then
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d1.divisor <= std_ulogic_vector(- signed(rb));
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else
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d1.divisor <= rb;
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end if;
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if ra(63) = rb(63) then
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d1.neg_result <= '0';
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else
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d1.neg_result <= '1';
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end if;
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '1';
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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@ -383,7 +338,7 @@ begin
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 64 loop
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for j in 0 to 65 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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@ -391,12 +346,15 @@ begin
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end loop;
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assert d2.valid = '1';
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if unsigned(d1.divisor(31 downto 0)) > unsigned(d1.dividend(63 downto 32)) then
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if rb /= x"0000000000000000" then
|
||||
behave_rt := std_ulogic_vector(signed(ra) / signed(rb));
|
||||
assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0)
|
||||
report "bad divwe expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
|
||||
assert ppc_cmpi('0', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
||||
report "bad CR setting for divwe";
|
||||
if behave_rt(63 downto 31) = x"00000000" & '0' or
|
||||
behave_rt(63 downto 31) = x"ffffffff" & '1' then
|
||||
assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0)
|
||||
report "bad divwe expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
|
||||
assert ppc_cmpi('0', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
||||
report "bad CR setting for divwe";
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
end loop;
|
||||
@ -412,7 +370,7 @@ begin
|
||||
|
||||
d1.dividend <= ra;
|
||||
d1.divisor <= rb;
|
||||
d1.neg_result <= '0';
|
||||
d1.is_signed <= '0';
|
||||
d1.is_extended <= '0';
|
||||
d1.is_32bit <= '1';
|
||||
d1.valid <= '1';
|
||||
@ -420,7 +378,7 @@ begin
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
for j in 0 to 65 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
@ -428,7 +386,7 @@ begin
|
||||
end loop;
|
||||
assert d2.valid = '1';
|
||||
|
||||
if unsigned(d1.divisor(31 downto 0)) > unsigned(d1.dividend(63 downto 32)) then
|
||||
if unsigned(rb(31 downto 0)) > unsigned(ra(63 downto 32)) then
|
||||
behave_rt := std_ulogic_vector(unsigned(ra) / unsigned(rb));
|
||||
assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0)
|
||||
report "bad divweu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
|
||||
@ -447,17 +405,9 @@ begin
|
||||
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
|
||||
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
|
||||
|
||||
if ra(63) = '1' then
|
||||
d1.dividend <= std_ulogic_vector(- signed(ra));
|
||||
else
|
||||
d1.dividend <= ra;
|
||||
end if;
|
||||
if rb(63) = '1' then
|
||||
d1.divisor <= std_ulogic_vector(- signed(rb));
|
||||
else
|
||||
d1.divisor <= rb;
|
||||
end if;
|
||||
d1.neg_result <= ra(63);
|
||||
d1.dividend <= ra;
|
||||
d1.divisor <= rb;
|
||||
d1.is_signed <= '1';
|
||||
d1.is_extended <= '0';
|
||||
d1.is_32bit <= '0';
|
||||
d1.is_modulus <= '1';
|
||||
@ -466,7 +416,7 @@ begin
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
for j in 0 to 65 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
@ -495,7 +445,7 @@ begin
|
||||
|
||||
d1.dividend <= ra;
|
||||
d1.divisor <= rb;
|
||||
d1.neg_result <= '0';
|
||||
d1.is_signed <= '0';
|
||||
d1.is_extended <= '0';
|
||||
d1.is_32bit <= '0';
|
||||
d1.is_modulus <= '1';
|
||||
@ -504,7 +454,7 @@ begin
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
for j in 0 to 65 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
@ -531,17 +481,9 @@ begin
|
||||
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
|
||||
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
|
||||
|
||||
if ra(63) = '1' then
|
||||
d1.dividend <= std_ulogic_vector(- signed(ra));
|
||||
else
|
||||
d1.dividend <= ra;
|
||||
end if;
|
||||
if rb(63) = '1' then
|
||||
d1.divisor <= std_ulogic_vector(- signed(rb));
|
||||
else
|
||||
d1.divisor <= rb;
|
||||
end if;
|
||||
d1.neg_result <= ra(63);
|
||||
d1.dividend <= ra;
|
||||
d1.divisor <= rb;
|
||||
d1.is_signed <= '1';
|
||||
d1.is_extended <= '0';
|
||||
d1.is_32bit <= '1';
|
||||
d1.is_modulus <= '1';
|
||||
@ -550,7 +492,7 @@ begin
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
for j in 0 to 65 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
@ -579,7 +521,7 @@ begin
|
||||
|
||||
d1.dividend <= ra;
|
||||
d1.divisor <= rb;
|
||||
d1.neg_result <= '0';
|
||||
d1.is_signed <= '0';
|
||||
d1.is_extended <= '0';
|
||||
d1.is_32bit <= '1';
|
||||
d1.is_modulus <= '1';
|
||||
@ -588,7 +530,7 @@ begin
|
||||
wait for clk_period;
|
||||
|
||||
d1.valid <= '0';
|
||||
for j in 0 to 64 loop
|
||||
for j in 0 to 65 loop
|
||||
wait for clk_period;
|
||||
if d2.valid = '1' then
|
||||
exit;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user