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divider: Always compute result/sresult/d_out.write_reg_data

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These are intended to be combinatorial.  The previous code was giving
warnings in vivado about registers/latches with no clock defined.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras 2019-09-25 20:03:46 +10:00
parent ad040601e6
commit e6536d4b8b
1 changed files with 12 additions and 11 deletions
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23
divider.vhdl
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@ -108,20 +108,21 @@ begin
d_out <= DividerToWritebackInit;
d_out.write_reg_nr <= write_reg;
if is_modulus = '1' then
result <= dend(127 downto 64);
else
result <= quot;
end if;
if neg_result = '1' then
sresult <= std_ulogic_vector(- signed(result));
else
sresult <= result;
end if;
d_out.write_reg_data <= sresult;
if count(6) = '1' then
d_out.valid <= '1';
d_out.write_reg_enable <= '1';
if is_modulus = '1' then
result <= dend(127 downto 64);
else
result <= quot;
end if;
if neg_result = '1' then
sresult <= std_ulogic_vector(- signed(result));
else
sresult <= result;
end if;
d_out.write_reg_data <= sresult;
if rc = '1' then
d_out.write_cr_enable <= '1';
d_out.write_cr_mask <= num_to_fxm(0);