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Fix yosys build after MMU merge

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
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Anton Blanchard
2020-05-19 11:22:29 +10:00
committed by Anton Blanchard
parent 9287e80711
commit 2aae3bf7a4
1 changed files with 1 additions and 1 deletions
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Makefile.synth
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@@ -45,7 +45,7 @@ OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
VHDL_FILES = fpga/soc_reset.vhdl fpga/clk_gen_bypass.vhd decode_types.vhdl
VHDL_FILES += common.vhdl wishbone_types.vhdl wishbone_debug_master.vhdl
VHDL_FILES += wishbone_arbiter.vhdl cache_ram.vhdl utils.vhdl plru.vhdl
VHDL_FILES += helpers.vhdl dcache.vhdl core_debug.vhdl fetch1.vhdl fetch2.vhdl
VHDL_FILES += helpers.vhdl mmu.vhdl dcache.vhdl core_debug.vhdl fetch1.vhdl fetch2.vhdl
VHDL_FILES += register_file.vhdl insn_helpers.vhdl multiply.vhdl divider.vhdl
VHDL_FILES += logical.vhdl crhelpers.vhdl countzero.vhdl rotator.vhdl
VHDL_FILES += ppc_fx_insns.vhdl execute1.vhdl decode1.vhdl cr_file.vhdl