mirror of
https://github.com/antonblanchard/microwatt.git
synced 2026-03-08 03:29:30 +00:00
SPI fixes, and remove reset controller and PLL
We need to expose all the input, output and output enable SPI lines in order to use QSPI. Remove the reset controller and PLL, since we are driving these directly from caravel.
This commit is contained in:
Anton Blanchard
committed by
Anton Blanchard
Anton Blanchard
parent
c87b883a82
commit
2e3668f840
@@ -15,9 +15,9 @@ entity toplevel is
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HAS_FPU : boolean := false;
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NO_BRAM : boolean := false;
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DISABLE_FLATTEN_CORE : boolean := false;
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SPI_FLASH_OFFSET : integer := 4194304;
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SPI_FLASH_DEF_CKDV : natural := 1;
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SPI_FLASH_DEF_QUAD : boolean := true;
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SPI_FLASH_OFFSET : integer := 0;
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SPI_FLASH_DEF_CKDV : natural := 4;
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SPI_FLASH_DEF_QUAD : boolean := false;
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LOG_LENGTH : natural := 16;
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UART_IS_16550 : boolean := true;
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HAS_UART1 : boolean := false;
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@@ -36,12 +36,11 @@ entity toplevel is
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uart1_rxd : in std_ulogic;
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-- SPI
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spi_flash_cs_n : out std_ulogic;
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spi_flash_clk : out std_ulogic;
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spi_flash_mosi : inout std_ulogic;
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spi_flash_miso : inout std_ulogic;
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spi_flash_wp_n : inout std_ulogic;
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spi_flash_hold_n : inout std_ulogic;
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spi_flash_cs_n : out std_ulogic;
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spi_flash_clk : out std_ulogic;
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spi_flash_sdat_i : in std_ulogic_vector(3 downto 0);
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spi_flash_sdat_o : out std_ulogic_vector(3 downto 0);
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spi_flash_sdat_oe : out std_ulogic_vector(3 downto 0);
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-- JTAG signals:
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jtag_tck : in std_ulogic;
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@@ -64,21 +63,14 @@ entity toplevel is
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end entity toplevel;
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architecture behaviour of toplevel is
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-- reset signals
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signal system_rst : std_ulogic;
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-- Reset signals:
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signal soc_rst : std_ulogic;
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signal pll_rst : std_ulogic;
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-- Internal clock signals:
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signal system_clk : std_ulogic;
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signal system_clk_locked : std_ulogic;
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signal ext_rst_n : std_ulogic;
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-- wishbone over logic analyzer connection
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-- external bus wishbone connection
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signal wb_dram_out : wishbone_master_out;
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signal wb_dram_in : wishbone_slave_out;
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-- Wishbone over LA
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-- external bus
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signal wb_mc_adr : wishbone_addr_type;
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signal wb_mc_dat_o : wishbone_data_type;
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signal wb_mc_cyc : std_ulogic;
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@@ -88,16 +80,10 @@ architecture behaviour of toplevel is
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signal wb_mc_dat_i : wishbone_data_type;
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signal wb_mc_ack : std_ulogic;
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signal wb_mc_stall : std_ulogic;
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-- SPI flash
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signal spi_sck : std_ulogic;
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signal spi_cs_n : std_ulogic;
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signal spi_sdat_o : std_ulogic_vector(3 downto 0);
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signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
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signal spi_sdat_i : std_ulogic_vector(3 downto 0);
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begin
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system_rst <= not ext_rst when RESET_LOW else ext_rst;
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-- Main SoC
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soc0: entity work.soc
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generic map(
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@@ -122,8 +108,8 @@ begin
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)
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port map (
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-- System signals
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system_clk => system_clk,
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rst => soc_rst,
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system_clk => ext_clk,
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rst => system_rst,
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-- UART signals
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uart0_txd => uart0_txd,
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@@ -134,11 +120,11 @@ begin
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uart1_rxd => uart1_rxd,
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-- SPI signals
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spi_flash_sck => spi_sck,
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spi_flash_cs_n => spi_cs_n,
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spi_flash_sdat_o => spi_sdat_o,
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spi_flash_sdat_oe => spi_sdat_oe,
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spi_flash_sdat_i => spi_sdat_i,
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spi_flash_sck => spi_flash_clk,
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spi_flash_cs_n => spi_flash_cs_n,
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spi_flash_sdat_o => spi_flash_sdat_o,
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spi_flash_sdat_oe => spi_flash_sdat_oe,
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spi_flash_sdat_i => spi_flash_sdat_i,
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-- JTAG signals
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jtag_tck => jtag_tck,
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@@ -155,8 +141,6 @@ begin
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alt_reset => alt_reset
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);
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ext_rst_n <= not ext_rst;
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mc0: entity work.mc
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generic map(
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WB_AW => 32, -- wishbone_addr_bits
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@@ -168,8 +152,8 @@ begin
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-- chunk at top for config space.
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)
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port map (
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clk => system_clk,
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rst => ext_rst_n,
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clk => ext_clk,
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rst => system_rst,
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wb_cyc => wb_mc_cyc,
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wb_stb => wb_mc_stb,
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@@ -190,19 +174,7 @@ begin
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-- int => ob int
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);
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-- SPI Flash
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spi_flash_cs_n <= spi_cs_n;
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spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
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spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
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spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
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spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
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spi_sdat_i(0) <= spi_flash_mosi;
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spi_sdat_i(1) <= spi_flash_miso;
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spi_sdat_i(2) <= spi_flash_wp_n;
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spi_sdat_i(3) <= spi_flash_hold_n;
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spi_flash_clk <= spi_sck;
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-- Wishbone over LA
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-- External bus wishbone
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wb_mc_adr <= wb_dram_out.adr;
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wb_mc_dat_o <= wb_dram_out.dat;
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wb_mc_cyc <= wb_dram_out.cyc;
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@@ -214,29 +186,4 @@ begin
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wb_dram_in.ack <= wb_mc_ack;
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wb_dram_in.stall <= wb_mc_stall;
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked,
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ext_rst_in => ext_rst,
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pll_rst_out => pll_rst,
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rst_out => soc_rst
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);
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clkgen: entity work.clock_generator
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generic map(
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CLK_INPUT_HZ => CLK_INPUT,
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CLK_OUTPUT_HZ => CLK_FREQUENCY
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)
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port map(
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ext_clk => ext_clk,
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pll_rst_in => pll_rst,
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pll_clk_out => system_clk,
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pll_locked_out => system_clk_locked
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);
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end architecture behaviour;
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