mirror of
https://github.com/antonblanchard/microwatt.git
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ECPIX-5: Add litedram support
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
parent
8e9ec4d1b7
commit
2e8dc3f449
1
Makefile
1
Makefile
@ -226,6 +226,7 @@ NEXTPNR_FLAGS=--um5g-85k --speed 8 --freq 50 --timing-allow-fail --ignore-loops
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OPENOCD_JTAG_CONFIG=openocd/ecpix-5.cfg
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OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
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toplevel=fpga/top-ecpix5.vhdl
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litedram_target=ecpix-5
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dmi_dtm=dmi_dtm_ecp5.vhdl
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endif
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@ -58,6 +58,107 @@ IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "spi_flash_hold_n" SITE "AE1";
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IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33;
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// DDR3 SDRAM
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LOCATE COMP "ddram_a[0]" SITE "T5";
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LOCATE COMP "ddram_a[1]" SITE "M3";
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LOCATE COMP "ddram_a[2]" SITE "L3";
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LOCATE COMP "ddram_a[3]" SITE "V6";
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LOCATE COMP "ddram_a[4]" SITE "K2";
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LOCATE COMP "ddram_a[5]" SITE "W6";
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LOCATE COMP "ddram_a[6]" SITE "K3";
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LOCATE COMP "ddram_a[7]" SITE "L1";
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LOCATE COMP "ddram_a[8]" SITE "H2";
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LOCATE COMP "ddram_a[9]" SITE "L2";
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LOCATE COMP "ddram_a[10]" SITE "N1";
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LOCATE COMP "ddram_a[11]" SITE "J1";
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LOCATE COMP "ddram_a[12]" SITE "M1";
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LOCATE COMP "ddram_a[13]" SITE "K1";
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LOCATE COMP "ddram_a[14]" SITE "H1";
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IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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LOCATE COMP "ddram_ba[0]" SITE "U6";
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LOCATE COMP "ddram_ba[1]" SITE "N3";
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LOCATE COMP "ddram_ba[2]" SITE "N4";
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LOCATE COMP "ddram_ras_n" SITE "T3";
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LOCATE COMP "ddram_cas_n" SITE "P2";
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LOCATE COMP "ddram_we_n" SITE "R3";
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LOCATE COMP "ddram_dm[0]" SITE "U4";
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LOCATE COMP "ddram_dm[1]" SITE "U1";
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IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_we_n" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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LOCATE COMP "ddram_dq[0]" SITE "T4";
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LOCATE COMP "ddram_dq[1]" SITE "W4";
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LOCATE COMP "ddram_dq[2]" SITE "R4";
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LOCATE COMP "ddram_dq[3]" SITE "W5";
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LOCATE COMP "ddram_dq[4]" SITE "R6";
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LOCATE COMP "ddram_dq[5]" SITE "P6";
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LOCATE COMP "ddram_dq[6]" SITE "P5";
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LOCATE COMP "ddram_dq[7]" SITE "P4";
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LOCATE COMP "ddram_dq[8]" SITE "R1";
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LOCATE COMP "ddram_dq[9]" SITE "W3";
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LOCATE COMP "ddram_dq[10]" SITE "T2";
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LOCATE COMP "ddram_dq[11]" SITE "V3";
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LOCATE COMP "ddram_dq[12]" SITE "U3";
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LOCATE COMP "ddram_dq[13]" SITE "W1";
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LOCATE COMP "ddram_dq[14]" SITE "T1";
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LOCATE COMP "ddram_dq[15]" SITE "W2";
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IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL15_I SLEWRATE=FAST TERMINATION=75;
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LOCATE COMP "ddram_dqs_n[0]" SITE "U5";
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LOCATE COMP "ddram_dqs_n[1]" SITE "U2";
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LOCATE COMP "ddram_dqs_p[0]" SITE "V4";
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LOCATE COMP "ddram_dqs_p[1]" SITE "V1";
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IOBUF PORT "ddram_dqs_n[0]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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IOBUF PORT "ddram_dqs_n[1]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL15D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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LOCATE COMP "ddram_clk_p" SITE "H3";
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LOCATE COMP "ddram_clk_n" SITE "J3";
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IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL15D_I SLEWRATE=FAST;
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IOBUF PORT "ddram_clk_n" IO_TYPE=SSTL15D_I SLEWRATE=FAST;
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LOCATE COMP "ddram_cke" SITE "P1";
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LOCATE COMP "ddram_odt" SITE "P3";
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IOBUF PORT "ddram_cke" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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IOBUF PORT "ddram_odt" IO_TYPE=SSTL15_I SLEWRATE=FAST;
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// PMOD signals
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LOCATE COMP "pmod0_0" SITE "T25";
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IOBUF PORT "pmod0_0" IO_TYPE=LVCMOS33;
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@ -14,8 +14,8 @@ entity toplevel is
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CLK_FREQUENCY : positive := 50000000;
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HAS_FPU : boolean := false;
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HAS_BTC : boolean := false;
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USE_LITEDRAM : boolean := false;
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NO_BRAM : boolean := false;
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USE_LITEDRAM : boolean := true;
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NO_BRAM : boolean := true;
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SCLK_STARTUPE2 : boolean := false;
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SPI_FLASH_OFFSET : integer := 4194304;
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SPI_FLASH_DEF_CKDV : natural := 0;
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@ -121,8 +121,23 @@ entity toplevel is
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pmod7_4 : inout std_ulogic;
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pmod7_5 : inout std_ulogic;
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pmod7_6 : inout std_ulogic;
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pmod7_7 : inout std_ulogic
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pmod7_7 : inout std_ulogic;
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-- DRAM wires
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ddram_a : out std_ulogic_vector(14 downto 0);
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ddram_ba : out std_ulogic_vector(2 downto 0);
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ddram_ras_n : out std_ulogic;
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ddram_cas_n : out std_ulogic;
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ddram_we_n : out std_ulogic;
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ddram_dm : out std_ulogic_vector(1 downto 0);
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ddram_dq : inout std_ulogic_vector(15 downto 0);
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ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
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ddram_clk_p : out std_ulogic_vector(0 downto 0);
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-- only the positive differential pin is instantiated
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--ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
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--ddram_clk_n : out std_ulogic_vector(0 downto 0);
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ddram_cke : out std_ulogic;
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ddram_odt : out std_ulogic
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);
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end entity toplevel;
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@ -136,6 +151,19 @@ architecture behaviour of toplevel is
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signal system_clk : std_ulogic;
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signal system_clk_locked : std_ulogic;
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-- External IOs from the SoC
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signal wb_ext_io_in : wb_io_master_out;
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signal wb_ext_io_out : wb_io_slave_out;
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signal wb_ext_is_dram_csr : std_ulogic;
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signal wb_ext_is_dram_init : std_ulogic;
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-- DRAM main data wishbone connection
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signal wb_dram_in : wishbone_master_out;
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signal wb_dram_out : wishbone_slave_out;
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-- DRAM control wishbone connection
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signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
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-- SPI flash
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signal spi_sck : std_ulogic;
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signal spi_sck_ts : std_ulogic;
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@ -215,7 +243,17 @@ begin
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spi_flash_cs_n => spi_cs_n,
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spi_flash_sdat_o => spi_sdat_o,
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spi_flash_sdat_oe => spi_sdat_oe,
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spi_flash_sdat_i => spi_sdat_i
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spi_flash_sdat_i => spi_sdat_i,
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-- DRAM wishbone
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wb_dram_in => wb_dram_in,
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wb_dram_out => wb_dram_out,
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-- IO wishbone
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wb_ext_io_in => wb_ext_io_in,
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wb_ext_io_out => wb_ext_io_out,
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wb_ext_is_dram_csr => wb_ext_is_dram_csr,
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wb_ext_is_dram_init => wb_ext_is_dram_init
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);
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-- SPI Flash
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@ -262,19 +300,108 @@ begin
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system_clk <= div2;
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system_clk_locked <= '1';
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led8_r_n <= '1';
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led8_g_n <= '1';
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led8_b_n <= '1';
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end generate;
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led5_r_n <= '0';
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has_dram: if USE_LITEDRAM generate
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signal dram_init_done : std_ulogic;
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signal dram_init_error : std_ulogic;
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signal dram_sys_rst : std_ulogic;
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begin
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-- Eventually dig out the frequency from
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-- litesdram generate.py sys_clk_freq
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-- but for now, assert it's 50Mhz for ECPIX-5
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assert CLK_FREQUENCY = 50000000;
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW,
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PLL_RESET_BITS => 18,
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SOC_RESET_BITS => 20
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked and not dram_sys_rst,
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ext_rst_in => ext_rst_n and gsrn,
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pll_rst_out => pll_rst,
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rst_out => soc_rst
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);
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-- Generate SoC reset
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soc_rst_gen: process(system_clk)
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begin
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if ext_rst_n = '0' then
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soc_rst <= '1';
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elsif rising_edge(system_clk) then
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soc_rst <= dram_sys_rst or not system_clk_locked;
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end if;
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end process;
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dram: entity work.litedram_wrapper
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generic map(
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DRAM_ABITS => 25,
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DRAM_ALINES => 15,
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DRAM_DLINES => 16,
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DRAM_CKLINES => 1,
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DRAM_PORT_WIDTH => 128,
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PAYLOAD_FILE => RAM_INIT_FILE,
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PAYLOAD_SIZE => PAYLOAD_SIZE
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)
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port map(
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clk_in => ext_clk,
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rst => pll_rst,
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system_clk => system_clk,
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system_reset => dram_sys_rst,
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pll_locked => system_clk_locked,
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wb_in => wb_dram_in,
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wb_out => wb_dram_out,
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wb_ctrl_in => wb_ext_io_in,
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wb_ctrl_out => wb_dram_ctrl_out,
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wb_ctrl_is_csr => wb_ext_is_dram_csr,
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wb_ctrl_is_init => wb_ext_is_dram_init,
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init_done => dram_init_done,
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init_error => dram_init_error,
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ddram_a => ddram_a,
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ddram_ba => ddram_ba,
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ddram_ras_n => ddram_ras_n,
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ddram_cas_n => ddram_cas_n,
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ddram_we_n => ddram_we_n,
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ddram_dm => ddram_dm,
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ddram_dq => ddram_dq,
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ddram_dqs_p => ddram_dqs_p,
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ddram_clk_p => ddram_clk_p,
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-- only the positive differential pin is instantiated
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--ddram_dqs_n => ddram_dqs_n,
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--ddram_clk_n => ddram_clk_n,
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ddram_cke => ddram_cke,
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ddram_odt => ddram_odt
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);
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-- active-low outputs to the LED
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led8_b_n <= dram_init_done;
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led8_r_n <= not dram_init_error;
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led8_g_n <= not (dram_init_done and not dram_init_error);
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end generate;
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-- Mux WB response on the IO bus
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wb_ext_io_out <= wb_dram_ctrl_out;
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led5_r_n <= '1';
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led5_g_n <= '1';
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led5_b_n <= '1';
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led6_r_n <= '1';
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led6_g_n <= '0';
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led6_g_n <= '1';
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led6_b_n <= '1';
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led7_r_n <= '1';
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led7_g_n <= '1';
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led7_b_n <= '0';
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led8_r_n <= '1';
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led8_g_n <= '1';
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led8_b_n <= '1';
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led7_r_n <= not soc_rst;
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led7_g_n <= not system_clk_locked;
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led7_b_n <= '1';
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end architecture behaviour;
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34
litedram/gen-src/ecpix-5.yml
Normal file
34
litedram/gen-src/ecpix-5.yml
Normal file
@ -0,0 +1,34 @@
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# Based on orangecrab-85-0.2.yml and arty.yml
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{
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"cpu": "None", # CPU type (ex vexriscv, serv, None)
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"device": "LFE5UM5G-85F-8BG554I",
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"memtype": "DDR3", # DRAM type
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"cmd_latency": 0,
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"sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM
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"sdram_module_nb": 2, # Number of byte groups
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"sdram_rank_nb": 1, # Number of ranks
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"sdram_phy": "ECP5DDRPHY", # Type of FPGA PHY
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# Electrical ---------------------------------------------------------------
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"rtt_nom": "60ohm", # Nominal termination. (Default)
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"rtt_wr": "60ohm", # Write termination. (Default)
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"ron": "34ohm", # Output driver impedance. (Default)
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# Frequency ----------------------------------------------------------------
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"input_clk_freq": 100e6, # Input clock frequency
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"sys_clk_freq": 50e6, # System clock frequency (DDR_clk = 4 x sys_clk)
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"init_clk_freq": 50e6, # ?
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# Core ---------------------------------------------------------------------
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"cmd_buffer_depth": 16, # Depth of the command buffer
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# User Ports ---------------------------------------------------------------
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"user_ports": {
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"native_0": {
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"type": "native",
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"block_until_ready": False,
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},
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},
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}
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@ -100,7 +100,8 @@ def generate_one(t):
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def main():
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targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'wukong-v2', 'orangecrab-85-0.2', 'sim']
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targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'wukong-v2', 'orangecrab-85-0.2',
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'ecpix-5', 'sim']
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for t in targets:
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generate_one(t)
|
||||
|
||||
|
||||
123
litedram/generated/ecpix-5/litedram-initmem.vhdl
Normal file
123
litedram/generated/ecpix-5/litedram-initmem.vhdl
Normal file
@ -0,0 +1,123 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
use work.utils.all;
|
||||
|
||||
entity dram_init_mem is
|
||||
generic (
|
||||
EXTRA_PAYLOAD_FILE : string := "";
|
||||
EXTRA_PAYLOAD_SIZE : integer := 0
|
||||
);
|
||||
port (
|
||||
clk : in std_ulogic;
|
||||
wb_in : in wb_io_master_out;
|
||||
wb_out : out wb_io_slave_out
|
||||
);
|
||||
end entity dram_init_mem;
|
||||
|
||||
architecture rtl of dram_init_mem is
|
||||
|
||||
constant INIT_RAM_SIZE : integer := 24576;
|
||||
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
|
||||
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
|
||||
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
|
||||
constant INIT_RAM_FILE : string := "litedram_core.init";
|
||||
|
||||
type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
|
||||
|
||||
-- XXX FIXME: Have a single init function called twice with
|
||||
-- an offset as argument
|
||||
procedure init_load_payload(ram: inout ram_t; filename: string) is
|
||||
file payload_file : text open read_mode is filename;
|
||||
variable ram_line : line;
|
||||
variable temp_word : std_logic_vector(63 downto 0);
|
||||
begin
|
||||
for i in 0 to RND_PAYLOAD_SIZE-1 loop
|
||||
exit when endfile(payload_file);
|
||||
readline(payload_file, ram_line);
|
||||
hread(ram_line, temp_word);
|
||||
ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0);
|
||||
ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32);
|
||||
end loop;
|
||||
assert endfile(payload_file) report "Payload too big !" severity failure;
|
||||
end procedure;
|
||||
|
||||
impure function init_load_ram(name : string) return ram_t is
|
||||
file ram_file : text open read_mode is name;
|
||||
variable temp_word : std_logic_vector(63 downto 0);
|
||||
variable temp_ram : ram_t := (others => (others => '0'));
|
||||
variable ram_line : line;
|
||||
begin
|
||||
report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) &
|
||||
" rounded to:" & integer'image(RND_PAYLOAD_SIZE);
|
||||
report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) &
|
||||
" bytes using " & integer'image(INIT_RAM_ABITS) &
|
||||
" address bits";
|
||||
for i in 0 to (INIT_RAM_SIZE/8)-1 loop
|
||||
exit when endfile(ram_file);
|
||||
readline(ram_file, ram_line);
|
||||
hread(ram_line, temp_word);
|
||||
temp_ram(i*2) := temp_word(31 downto 0);
|
||||
temp_ram(i*2+1) := temp_word(63 downto 32);
|
||||
end loop;
|
||||
if RND_PAYLOAD_SIZE /= 0 then
|
||||
init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE);
|
||||
end if;
|
||||
return temp_ram;
|
||||
end function;
|
||||
|
||||
impure function init_zero return ram_t is
|
||||
variable temp_ram : ram_t := (others => (others => '0'));
|
||||
begin
|
||||
return temp_ram;
|
||||
end function;
|
||||
|
||||
impure function initialize_ram(filename: string) return ram_t is
|
||||
begin
|
||||
report "Opening file " & filename;
|
||||
if filename'length = 0 then
|
||||
return init_zero;
|
||||
else
|
||||
return init_load_ram(filename);
|
||||
end if;
|
||||
end function;
|
||||
signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE);
|
||||
|
||||
attribute ram_style : string;
|
||||
attribute ram_style of init_ram: signal is "block";
|
||||
|
||||
signal obuf : std_ulogic_vector(31 downto 0);
|
||||
signal oack : std_ulogic;
|
||||
begin
|
||||
|
||||
init_ram_0: process(clk)
|
||||
variable adr : integer;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
oack <= '0';
|
||||
if (wb_in.cyc and wb_in.stb) = '1' then
|
||||
adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0))));
|
||||
if wb_in.we = '0' then
|
||||
obuf <= init_ram(adr);
|
||||
else
|
||||
for i in 0 to 3 loop
|
||||
if wb_in.sel(i) = '1' then
|
||||
init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
|
||||
wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
oack <= '1';
|
||||
end if;
|
||||
wb_out.ack <= oack;
|
||||
wb_out.dat <= obuf;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
wb_out.stall <= '0';
|
||||
|
||||
end architecture rtl;
|
||||
2002
litedram/generated/ecpix-5/litedram_core.init
Normal file
2002
litedram/generated/ecpix-5/litedram_core.init
Normal file
File diff suppressed because it is too large
Load Diff
14969
litedram/generated/ecpix-5/litedram_core.v
Normal file
14969
litedram/generated/ecpix-5/litedram_core.v
Normal file
File diff suppressed because one or more lines are too long
Loading…
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Reference in New Issue
Block a user