core: Improve core reset

The icache would still spit out an instruction which could
cause a 0x700 instead of a reset.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

control.vhdl

@@ -159,6 +159,13 @@ begin
             v_int.outstanding := r_int.outstanding - 1;
         end if;
 
+        if rst = '1' then
+            v_int.state := IDLE;
+            v_int.outstanding := 0;
+            stall_tmp := '0';
+            valid_tmp := '0';
+        end if;
+
         -- Handle debugger stop
         stopped_out <= '0';
         if stop_mark_in = '1' and v_int.outstanding = 0 then
@@ -228,12 +235,6 @@ begin
             cr_write_valid <= '0';
         end if;
 
-        if rst = '1' then
-            v_int.state := IDLE;
-            v_int.outstanding := 0;
-            stall_tmp := '0';
-        end if;
-
         -- update outputs
         valid_out <= valid_tmp;
         stall_out <= stall_tmp;

fetch2.vhdl

@@ -105,6 +105,7 @@ begin
 	-- Clear stash on reset
 	if rst = '1' then
 	    v_int.stash_valid := '0';
+            v.valid := '0';
 	end if;
 
 	-- Update registers

icache.vhdl

@@ -385,7 +385,7 @@ begin
 	end loop;
 
 	-- Generate the "hit" and "miss" signals for the synchronous blocks
-	req_is_hit  <= i_in.req and is_hit and not flush_in;
+	req_is_hit  <= i_in.req and is_hit and not flush_in and not rst;
 	req_is_miss <= i_in.req and not is_hit and not flush_in;
 	req_hit_way <= hit_way;