fpga: Hookup Arty to litedram

The old toplevel.vhdl becomes top-generic.vhdl, which is to be used by platforms that do not have a litedram option. Arty has its own top-arty.vhdl which supports litedram and is now hooked up Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2026-04-15 15:50:24 +00:00 · 2019-09-10 18:24:06 +01:00
parent 8bb3c8f8b6
commit 3ac815823c
4 changed files with 510 additions and 7 deletions
--- a/fpga/arty_a7.xdc
+++ b/fpga/arty_a7.xdc
@@ -1,10 +1,235 @@
-set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
+set_property -dict { PACKAGE_PIN E3  IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
 create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }];

-set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];
+set_property -dict { PACKAGE_PIN C2  IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];

-set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
-set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];
+set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }];
+set_property -dict { PACKAGE_PIN A9  IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }];
+
+##Pmod Header JC: UART (bottom)
+
+set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }];
+set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }];
+set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }];
+set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }];
+
+# LEDs
+set_property -dict { PACKAGE_PIN E1  IOSTANDARD LVCMOS33 } [get_ports { led0_b }];
+set_property -dict { PACKAGE_PIN F6  IOSTANDARD LVCMOS33 } [get_ports { led0_g }];
+set_property -dict { PACKAGE_PIN G6  IOSTANDARD LVCMOS33 } [get_ports { led0_r }];
+
+# DRAM (generated by LiteX)
+ ## ddram:0.a
+set_property LOC R2 [get_ports ddram_a[0]]
+set_property SLEW FAST [get_ports ddram_a[0]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]]
+ ## ddram:0.a
+set_property LOC M6 [get_ports ddram_a[1]]
+set_property SLEW FAST [get_ports ddram_a[1]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]]
+ ## ddram:0.a
+set_property LOC N4 [get_ports ddram_a[2]]
+set_property SLEW FAST [get_ports ddram_a[2]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]]
+ ## ddram:0.a
+set_property LOC T1 [get_ports ddram_a[3]]
+set_property SLEW FAST [get_ports ddram_a[3]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]]
+ ## ddram:0.a
+set_property LOC N6 [get_ports ddram_a[4]]
+set_property SLEW FAST [get_ports ddram_a[4]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]]
+ ## ddram:0.a
+set_property LOC R7 [get_ports ddram_a[5]]
+set_property SLEW FAST [get_ports ddram_a[5]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]]
+ ## ddram:0.a
+set_property LOC V6 [get_ports ddram_a[6]]
+set_property SLEW FAST [get_ports ddram_a[6]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]]
+ ## ddram:0.a
+set_property LOC U7 [get_ports ddram_a[7]]
+set_property SLEW FAST [get_ports ddram_a[7]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]]
+ ## ddram:0.a
+set_property LOC R8 [get_ports ddram_a[8]]
+set_property SLEW FAST [get_ports ddram_a[8]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]]
+ ## ddram:0.a
+set_property LOC V7 [get_ports ddram_a[9]]
+set_property SLEW FAST [get_ports ddram_a[9]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]]
+ ## ddram:0.a
+set_property LOC R6 [get_ports ddram_a[10]]
+set_property SLEW FAST [get_ports ddram_a[10]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]]
+ ## ddram:0.a
+set_property LOC U6 [get_ports ddram_a[11]]
+set_property SLEW FAST [get_ports ddram_a[11]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]]
+ ## ddram:0.a
+set_property LOC T6 [get_ports ddram_a[12]]
+set_property SLEW FAST [get_ports ddram_a[12]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]]
+ ## ddram:0.a
+set_property LOC T8 [get_ports ddram_a[13]]
+set_property SLEW FAST [get_ports ddram_a[13]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]]
+ ## ddram:0.ba
+set_property LOC R1 [get_ports ddram_ba[0]]
+set_property SLEW FAST [get_ports ddram_ba[0]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]]
+ ## ddram:0.ba
+set_property LOC P4 [get_ports ddram_ba[1]]
+set_property SLEW FAST [get_ports ddram_ba[1]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]]
+ ## ddram:0.ba
+set_property LOC P2 [get_ports ddram_ba[2]]
+set_property SLEW FAST [get_ports ddram_ba[2]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]]
+ ## ddram:0.ras_n
+set_property LOC P3 [get_ports ddram_ras_n]
+set_property SLEW FAST [get_ports ddram_ras_n]
+set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
+ ## ddram:0.cas_n
+set_property LOC M4 [get_ports ddram_cas_n]
+set_property SLEW FAST [get_ports ddram_cas_n]
+set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
+ ## ddram:0.we_n
+set_property LOC P5 [get_ports ddram_we_n]
+set_property SLEW FAST [get_ports ddram_we_n]
+set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
+ ## ddram:0.cs_n
+set_property LOC U8 [get_ports ddram_cs_n]
+set_property SLEW FAST [get_ports ddram_cs_n]
+set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
+ ## ddram:0.dm
+set_property LOC L1 [get_ports ddram_dm[0]]
+set_property SLEW FAST [get_ports ddram_dm[0]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]]
+ ## ddram:0.dm
+set_property LOC U1 [get_ports ddram_dm[1]]
+set_property SLEW FAST [get_ports ddram_dm[1]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]]
+ ## ddram:0.dq
+set_property LOC K5 [get_ports ddram_dq[0]]
+set_property SLEW FAST [get_ports ddram_dq[0]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
+ ## ddram:0.dq
+set_property LOC L3 [get_ports ddram_dq[1]]
+set_property SLEW FAST [get_ports ddram_dq[1]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
+ ## ddram:0.dq
+set_property LOC K3 [get_ports ddram_dq[2]]
+set_property SLEW FAST [get_ports ddram_dq[2]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
+ ## ddram:0.dq
+set_property LOC L6 [get_ports ddram_dq[3]]
+set_property SLEW FAST [get_ports ddram_dq[3]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
+ ## ddram:0.dq
+set_property LOC M3 [get_ports ddram_dq[4]]
+set_property SLEW FAST [get_ports ddram_dq[4]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
+ ## ddram:0.dq
+set_property LOC M1 [get_ports ddram_dq[5]]
+set_property SLEW FAST [get_ports ddram_dq[5]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
+ ## ddram:0.dq
+set_property LOC L4 [get_ports ddram_dq[6]]
+set_property SLEW FAST [get_ports ddram_dq[6]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
+ ## ddram:0.dq
+set_property LOC M2 [get_ports ddram_dq[7]]
+set_property SLEW FAST [get_ports ddram_dq[7]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
+ ## ddram:0.dq
+set_property LOC V4 [get_ports ddram_dq[8]]
+set_property SLEW FAST [get_ports ddram_dq[8]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
+ ## ddram:0.dq
+set_property LOC T5 [get_ports ddram_dq[9]]
+set_property SLEW FAST [get_ports ddram_dq[9]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
+ ## ddram:0.dq
+set_property LOC U4 [get_ports ddram_dq[10]]
+set_property SLEW FAST [get_ports ddram_dq[10]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
+ ## ddram:0.dq
+set_property LOC V5 [get_ports ddram_dq[11]]
+set_property SLEW FAST [get_ports ddram_dq[11]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
+ ## ddram:0.dq
+set_property LOC V1 [get_ports ddram_dq[12]]
+set_property SLEW FAST [get_ports ddram_dq[12]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
+ ## ddram:0.dq
+set_property LOC T3 [get_ports ddram_dq[13]]
+set_property SLEW FAST [get_ports ddram_dq[13]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
+ ## ddram:0.dq
+set_property LOC U3 [get_ports ddram_dq[14]]
+set_property SLEW FAST [get_ports ddram_dq[14]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
+ ## ddram:0.dq
+set_property LOC R3 [get_ports ddram_dq[15]]
+set_property SLEW FAST [get_ports ddram_dq[15]]
+set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
+ ## ddram:0.dqs_p
+set_property LOC N2 [get_ports ddram_dqs_p[0]]
+set_property SLEW FAST [get_ports ddram_dqs_p[0]]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]]
+ ## ddram:0.dqs_p
+set_property LOC U2 [get_ports ddram_dqs_p[1]]
+set_property SLEW FAST [get_ports ddram_dqs_p[1]]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]]
+ ## ddram:0.dqs_n
+set_property LOC N1 [get_ports ddram_dqs_n[0]]
+set_property SLEW FAST [get_ports ddram_dqs_n[0]]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]]
+ ## ddram:0.dqs_n
+set_property LOC V2 [get_ports ddram_dqs_n[1]]
+set_property SLEW FAST [get_ports ddram_dqs_n[1]]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]]
+ ## ddram:0.clk_p
+set_property LOC U9 [get_ports ddram_clk_p]
+set_property SLEW FAST [get_ports ddram_clk_p]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
+ ## ddram:0.clk_n
+set_property LOC V9 [get_ports ddram_clk_n]
+set_property SLEW FAST [get_ports ddram_clk_n]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
+ ## ddram:0.cke
+set_property LOC N5 [get_ports ddram_cke]
+set_property SLEW FAST [get_ports ddram_cke]
+set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
+ ## ddram:0.odt
+set_property LOC R5 [get_ports ddram_odt]
+set_property SLEW FAST [get_ports ddram_odt]
+set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
+ ## ddram:0.reset_n
+set_property LOC K6 [get_ports ddram_reset_n]
+set_property SLEW FAST [get_ports ddram_reset_n]
+set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
+
+#Internal VREF
+set_property INTERNAL_VREF 0.675 [get_iobanks 34]

 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property CFGBVS VCCO [current_design]
--- a/fpga/top-arty.vhdl
+++ b/fpga/top-arty.vhdl
@@ -0,0 +1,244 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity toplevel is
+    generic (
+	MEMORY_SIZE   : positive := 16384;
+	RAM_INIT_FILE : string   := "firmware.hex";
+	RESET_LOW     : boolean  := true;
+	CLK_FREQUENCY : positive := 100000000;
+	USE_LITEDRAM  : boolean  := false;
+	DISABLE_FLATTEN_CORE : boolean := false
+	);
+    port(
+	ext_clk   : in  std_ulogic;
+	ext_rst   : in  std_ulogic;
+
+	-- UART0 signals:
+	uart_main_tx : out std_ulogic;
+	uart_main_rx : in  std_ulogic;
+
+	-- DRAM UART signals (PMOD)
+	uart_pmod_tx    : out std_ulogic;
+	uart_pmod_rx    : in std_ulogic;
+	uart_pmod_cts_n : in std_ulogic;
+	uart_pmod_rts_n : out std_ulogic;
+
+	-- LEDs
+	led0_b	: out std_ulogic;
+	led0_g	: out std_ulogic;
+	led0_r	: out std_ulogic;
+
+	-- DRAM wires
+	ddram_a       : out std_ulogic_vector(13 downto 0);
+	ddram_ba      : out std_ulogic_vector(2 downto 0);
+	ddram_ras_n   : out std_ulogic;
+	ddram_cas_n   : out std_ulogic;
+	ddram_we_n    : out std_ulogic;
+	ddram_cs_n    : out std_ulogic;
+	ddram_dm      : out std_ulogic_vector(1 downto 0);
+	ddram_dq      : inout std_ulogic_vector(15 downto 0);
+	ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
+	ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
+	ddram_clk_p   : out std_ulogic;
+	ddram_clk_n   : out std_ulogic;
+	ddram_cke     : out std_ulogic;
+	ddram_odt     : out std_ulogic;
+	ddram_reset_n : out std_ulogic
+	);
+end entity toplevel;
+
+architecture behaviour of toplevel is
+
+    -- Reset signals:
+    signal soc_rst : std_ulogic;
+    signal pll_rst : std_ulogic;
+
+    -- Internal clock signals:
+    signal system_clk : std_ulogic;
+    signal system_clk_locked : std_ulogic;
+
+    -- DRAM wishbone connection
+    signal wb_dram_in   : wishbone_master_out;
+    signal wb_dram_out  : wishbone_slave_out;
+    signal wb_dram_csr  : std_ulogic;
+    signal wb_dram_init : std_ulogic;
+
+    -- Control/status
+    signal core_alt_reset : std_ulogic;
+
+    -- Status LED
+    signal led0_b_pwm : std_ulogic;
+    signal led0_r_pwm : std_ulogic;
+    signal led0_g_pwm : std_ulogic;
+
+    -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
+    signal pwm_counter  : std_ulogic_vector(8 downto 0);
+begin
+
+    uart_pmod_rts_n <= '0';
+
+    -- Main SoC
+    soc0: entity work.soc
+	generic map(
+	    MEMORY_SIZE   => MEMORY_SIZE,
+	    RAM_INIT_FILE => RAM_INIT_FILE,
+	    RESET_LOW     => RESET_LOW,
+	    SIM           => false,
+	    HAS_DRAM      => USE_LITEDRAM,
+	    DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE
+	    )
+	port map (
+	    system_clk        => system_clk,
+	    rst               => soc_rst,
+	    uart0_txd         => uart_main_tx,
+	    uart0_rxd         => uart_main_rx,
+	    wb_dram_in        => wb_dram_in,
+	    wb_dram_out       => wb_dram_out,
+	    wb_dram_csr       => wb_dram_csr,
+	    wb_dram_init      => wb_dram_init,
+	    alt_reset         => core_alt_reset
+	    );
+
+    nodram: if not USE_LITEDRAM generate
+        signal ddram_clk_dummy : std_ulogic;
+    begin
+	reset_controller: entity work.soc_reset
+	    generic map(
+		RESET_LOW => RESET_LOW
+		)
+	    port map(
+		ext_clk => ext_clk,
+		pll_clk => system_clk,
+		pll_locked_in => system_clk_locked,
+		ext_rst_in => ext_rst,
+		pll_rst_out => pll_rst,
+		rst_out => soc_rst
+		);
+
+	clkgen: entity work.clock_generator
+	    generic map(
+		CLK_INPUT_HZ => 100000000,
+		CLK_OUTPUT_HZ => CLK_FREQUENCY
+		)
+	    port map(
+		ext_clk => ext_clk,
+		pll_rst_in => pll_rst,
+		pll_clk_out => system_clk,
+		pll_locked_out => system_clk_locked
+		);
+
+	led0_b_pwm <= '1';
+	led0_r_pwm <= '1';
+	led0_g_pwm <= '0';
+        core_alt_reset <= '0';
+
+        -- Vivado barfs on those differential signals if left
+        -- unconnected. So instanciate a diff. buffer and feed
+        -- it a constant '0'.
+        dummy_dram_clk: OBUFDS
+            port map (
+                O => ddram_clk_p,
+                OB => ddram_clk_n,
+                I => ddram_clk_dummy
+                );
+        ddram_clk_dummy <= '0';
+
+   end generate;
+
+    has_dram: if USE_LITEDRAM generate
+        signal dram_init_done  : std_ulogic;
+	signal dram_init_error : std_ulogic;
+	signal soc_rst_0       : std_ulogic;
+	signal soc_rst_1       : std_ulogic;
+    begin
+
+	-- Eventually dig out the frequency from the generator
+	-- but for now, assert it's 100Mhz
+	assert CLK_FREQUENCY = 100000000;
+
+	reset_controller: entity work.soc_reset
+	    generic map(
+		RESET_LOW => RESET_LOW
+		)
+	    port map(
+		ext_clk => ext_clk,
+		pll_clk => system_clk,
+		pll_locked_in => system_clk_locked,
+		ext_rst_in => ext_rst,
+		pll_rst_out => pll_rst,
+		rst_out => soc_rst_0
+		);
+
+	dram: entity work.litedram_wrapper
+	    generic map(
+		DRAM_ABITS => 24,
+		DRAM_ALINES => 14
+		)
+	    port map(
+		clk_in		=> ext_clk,
+		rst             => pll_rst,
+		system_clk	=> system_clk,
+		system_reset	=> soc_rst_1,
+		core_alt_reset	=> core_alt_reset,
+		pll_locked	=> system_clk_locked,
+
+		wb_in		=> wb_dram_in,
+		wb_out		=> wb_dram_out,
+		wb_is_csr       => wb_dram_csr,
+		wb_is_init      => wb_dram_init,
+
+		serial_tx	=> uart_pmod_tx,
+		serial_rx	=> uart_pmod_rx,
+
+		init_done 	=> dram_init_done,
+		init_error	=> dram_init_error,
+
+		ddram_a		=> ddram_a,
+		ddram_ba	=> ddram_ba,
+		ddram_ras_n	=> ddram_ras_n,
+		ddram_cas_n	=> ddram_cas_n,
+		ddram_we_n	=> ddram_we_n,
+		ddram_cs_n	=> ddram_cs_n,
+		ddram_dm	=> ddram_dm,
+		ddram_dq	=> ddram_dq,
+		ddram_dqs_p	=> ddram_dqs_p,
+		ddram_dqs_n	=> ddram_dqs_n,
+		ddram_clk_p	=> ddram_clk_p,
+		ddram_clk_n	=> ddram_clk_n,
+		ddram_cke	=> ddram_cke,
+		ddram_odt	=> ddram_odt,
+		ddram_reset_n	=> ddram_reset_n
+		);
+
+	led0_b_pwm <= not dram_init_done;
+	led0_r_pwm <= dram_init_error;
+	led0_g_pwm <= dram_init_done and not dram_init_error;
+	soc_rst <= soc_rst_0 or soc_rst_1;
+
+    end generate;
+
+    leds_pwm : process(system_clk)
+    begin
+	if rising_edge(system_clk) then
+	    pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1);
+	    if pwm_counter(8 downto 4) = "00000" then
+		led0_b <= led0_b_pwm;
+		led0_r <= led0_r_pwm;
+		led0_g <= led0_g_pwm;
+	    else
+		led0_b <= '0';
+		led0_r <= '0';
+		led0_g <= '0';
+	    end if;
+	end if;
+    end process;
+
+end architecture behaviour;
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
--- a/microwatt.core
+++ b/microwatt.core
@@ -55,7 +55,6 @@ filesets:
      - fpga/pp_fifo.vhd
      - fpga/pp_soc_uart.vhd
      - fpga/pp_utilities.vhd
-      - fpga/toplevel.vhdl
      - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
    file_type : vhdlSource-2008

@@ -71,21 +70,25 @@ filesets:
    files:
      - fpga/nexys_a7.xdc : {file_type : xdc}
      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}

  nexys_video:
    files:
      - fpga/nexys-video.xdc : {file_type : xdc}
      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}

  arty_a7:
    files:
      - fpga/arty_a7.xdc : {file_type : xdc}
      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}

  cmod_a7-35:
    files:
      - fpga/cmod_a7-35.xdc : {file_type : xdc}
      - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}

  litedram:
      depend : [":microwatt:litedram"]
@@ -117,7 +120,7 @@ targets:
      vivado: {part : xc7a200tsbg484-1}
    toplevel : toplevel

-  arty_a7-35:
+  arty_a7-35-nodram:
    default_tool: vivado
    filesets: [core, arty_a7, soc, fpga, debug_xilinx]
    parameters :
@@ -130,7 +133,20 @@ targets:
      vivado: {part : xc7a35ticsg324-1L}
    toplevel : toplevel

-  arty_a7-100:
+  arty_a7-35:
+    default_tool: vivado
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
+    parameters :
+      - memory_size
+      - ram_init_file
+      - use_litedram=true
+      - disable_flatten_core
+    generate: [dram_arty]
+    tools:
+      vivado: {part : xc7a35ticsg324-1L}
+    toplevel : toplevel
+
+  arty_a7-100-nodram:
    default_tool: vivado
    filesets: [core, arty_a7, soc, fpga, debug_xilinx]
    parameters :
@@ -143,6 +159,19 @@ targets:
      vivado: {part : xc7a100ticsg324-1L}
    toplevel : toplevel

+  arty_a7-100:
+    default_tool: vivado
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
+    parameters:
+      - memory_size
+      - ram_init_file
+      - use_litedram=true
+      - disable_flatten_core
+    generate: [dram_arty]
+    tools:
+      vivado: {part : xc7a100ticsg324-1L}
+    toplevel : toplevel
+
  cmod_a7-35:
    default_tool: vivado
    filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
@@ -163,6 +192,11 @@ targets:
      vivado: {pnr : none}
    toplevel: core

+generate:
+  dram_arty:
+    generator: litedram_gen
+    parameters: {board : arty}
+
 parameters:
  memory_size:
    datatype    : int