Merge pull request #76 from antonblanchard/misc

Some misc updates

Makefile

@@ -16,7 +16,7 @@ common.o: decode_types.o
 sim_jtag.o: sim_jtag_socket.o
 core_tb.o: common.o wishbone_types.o core.o soc.o sim_jtag.o
 core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o writeback.o core_debug.o divider.o
-core_debug.o:
+core_debug.o: common.o
 cr_file.o: common.o
 crhelpers.o: common.o
 decode1.o: common.o decode_types.o
@@ -50,7 +50,7 @@ wishbone_arbiter.o: wishbone_types.o
 wishbone_types.o:
 writeback.o: common.o
 dmi_dtm_tb.o: dmi_dtm_xilinx.o wishbone_debug_master.o
-dmi_dtm_xilinx.o: sim-unisim/unisim_vcomponents.o
+dmi_dtm_xilinx.o: wishbone_types.o sim-unisim/unisim_vcomponents.o
 wishbone_debug_master.o: wishbone_types.o
 
 UNISIM_BITS = sim-unisim/unisim_vcomponents.vhdl sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl

common.vhdl

@@ -14,7 +14,16 @@ package common is
 
 	type Fetch1ToFetch2Type is record
 	    nia: std_ulogic_vector(63 downto 0);
-	    pipe_stop : std_ulogic;
+	end record;
+
+	type Fetch2ToIcacheType is record
+		req: std_ulogic;
+		addr: std_ulogic_vector(63 downto 0);
+	end record;
+
+	type IcacheToFetch2Type is record
+		ack: std_ulogic;
+		insn: std_ulogic_vector(31 downto 0);
 	end record;
 
 	type Fetch2ToDecode1Type is record
@@ -34,16 +43,6 @@ package common is
 	end record;
 	constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
 
-	type Fetch2ToIcacheType is record
-		req: std_ulogic;
-		addr: std_ulogic_vector(63 downto 0);
-	end record;
-
-	type IcacheToFetch2Type is record
-		ack: std_ulogic;
-		insn: std_ulogic_vector(31 downto 0);
-	end record;
-
 	type Decode2ToExecute1Type is record
 		valid: std_ulogic;
 		insn_type: insn_type_t;

execute1.vhdl

@@ -70,7 +70,6 @@ begin
 		ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 
 		terminate_out <= '0';
-		flush_out <= '0';
 		f_out <= Execute1ToFetch1TypeInit;
 
 		if e_in.valid = '1' then
@@ -100,7 +99,6 @@ begin
 					result := ppc_andc(e_in.read_data1, e_in.read_data2);
 					result_en := 1;
 				when OP_B =>
-					flush_out <= '1';
 					f_out.redirect <= '1';
 					f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(e_in.read_data2));
 				when OP_BC =>
@@ -108,7 +106,6 @@ begin
 						ctrl_tmp.ctr <= std_ulogic_vector(unsigned(ctrl.ctr) - 1);
 					end if;
 					if ppc_bc_taken(e_in.const1(4 downto 0), e_in.const2(4 downto 0), e_in.cr, ctrl.ctr) = 1 then
-						flush_out <= '1';
 						f_out.redirect <= '1';
 						f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(e_in.read_data2));
 					end if;
@@ -117,13 +114,11 @@ begin
 						ctrl_tmp.ctr <= std_ulogic_vector(unsigned(ctrl.ctr) - 1);
 					end if;
 					if ppc_bc_taken(e_in.const1(4 downto 0), e_in.const2(4 downto 0), e_in.cr, ctrl.ctr) = 1 then
-						flush_out <= '1';
 						f_out.redirect <= '1';
 						f_out.redirect_nia <= ctrl.lr(63 downto 2) & "00";
 					end if;
 				when OP_BCCTR =>
 					if ppc_bcctr_taken(e_in.const1(4 downto 0), e_in.const2(4 downto 0), e_in.cr) = 1 then
-						flush_out <= '1';
 						f_out.redirect <= '1';
 						f_out.redirect_nia <= ctrl.ctr(63 downto 2) & "00";
 					end if;
@@ -354,5 +349,6 @@ begin
 		-- update outputs
 		--f_out <= r.f;
 		e_out <= r.e;
+		flush_out <= f_out.redirect;
 	end process;
 end architecture behaviour;

fetch1.vhdl

@@ -6,70 +6,70 @@ library work;
 use work.common.all;
 
 entity fetch1 is
-	generic(
-		RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0')
+    generic(
+	RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0')
 	);
-	port(
-		clk           : in std_ulogic;
-		rst           : in std_ulogic;
+    port(
+	clk           : in std_ulogic;
+	rst           : in std_ulogic;
 
-		-- Control inputs:
-		stall_in      : in std_ulogic;
-		flush_in      : in std_ulogic;
+	-- Control inputs:
+	stall_in      : in std_ulogic;
+	flush_in      : in std_ulogic;
 
-		-- redirect from execution unit
-		e_in          : in Execute1ToFetch1Type;
+	-- redirect from execution unit
+	e_in          : in Execute1ToFetch1Type;
 
-		-- fetch data out
-		f_out         : out Fetch1ToFetch2Type
+	-- fetch data out
+	f_out         : out Fetch1ToFetch2Type
 	);
 end entity fetch1;
 
 architecture behaviour of fetch1 is
-	type reg_internal_type is record
-		nia_next : std_ulogic_vector(63 downto 0);
-	end record;
-	signal r_int, rin_int : reg_internal_type;
-	signal r, rin : Fetch1ToFetch2Type;
+    type reg_internal_type is record
+	nia_next : std_ulogic_vector(63 downto 0);
+    end record;
+    signal r_int, rin_int : reg_internal_type;
+    signal r, rin : Fetch1ToFetch2Type;
 begin
-	regs : process(clk)
-	begin
-		if rising_edge(clk) then
-			r <= rin;
-			r_int <= rin_int;
-		end if;
-	end process;
+    regs : process(clk)
+    begin
+	if rising_edge(clk) then
+	    r <= rin;
+	    r_int <= rin_int;
+	end if;
+    end process;
 
-	comb : process(all)
-		variable v     : Fetch1ToFetch2Type;
-		variable v_int : reg_internal_type;
-	begin
-		v := r;
-		v_int := r_int;
+    comb : process(all)
+	variable v     : Fetch1ToFetch2Type;
+	variable v_int : reg_internal_type;
+    begin
+	v := r;
+	v_int := r_int;
 
-		if stall_in = '0' then
-			v.nia := r_int.nia_next;
-			v_int.nia_next := std_logic_vector(unsigned(r_int.nia_next) + 4);
-		end if;
+	if stall_in = '0' then
+	    v.nia := r_int.nia_next;
+	end if;
 
-		if e_in.redirect = '1' then
-			v.nia := e_in.redirect_nia;
-			v_int.nia_next := std_logic_vector(unsigned(e_in.redirect_nia) + 4);
-		end if;
+	if e_in.redirect = '1' then
+	    v.nia := e_in.redirect_nia;
+	end if;
 
-		if rst = '1' then
-			v.nia := RESET_ADDRESS;
-			v_int.nia_next := std_logic_vector(unsigned(RESET_ADDRESS) + 4);
-		end if;
+	if rst = '1' then
+	    v.nia := RESET_ADDRESS;
+	end if;
 
-		-- Update registers
-		rin <= v;
-		rin_int <= v_int;
+	v_int.nia_next := std_logic_vector(unsigned(v.nia) + 4);
 
-		-- Update outputs
-		f_out <= r;
+	-- Update registers
+	rin <= v;
+	rin_int <= v_int;
 
-		report "fetch1 R:" & std_ulogic'image(e_in.redirect) & " v.nia:" & to_hstring(v.nia) & " f_out.nia:" & to_hstring(f_out.nia);
-	end process;
+	-- Update outputs
+	f_out <= r;
+
+	report "fetch1 R:" & std_ulogic'image(e_in.redirect) & " v.nia:" & to_hstring(v.nia) & " f_out.nia:" & to_hstring(f_out.nia);
+
+    end process;
 
 end architecture behaviour;

fetch2.vhdl

@@ -7,60 +7,60 @@ use work.common.all;
 use work.wishbone_types.all;
 
 entity fetch2 is
-	port(
-		clk          : in std_ulogic;
-		rst          : in std_ulogic;
+    port(
+	clk          : in std_ulogic;
+	rst          : in std_ulogic;
 
-		stall_in     : in std_ulogic;
-		stall_out    : out std_ulogic;
+	stall_in     : in std_ulogic;
+	stall_out    : out std_ulogic;
 
-		flush_in     : in std_ulogic;
-		stop_in      : in std_ulogic;
+	flush_in     : in std_ulogic;
+	stop_in      : in std_ulogic;
 
-		i_in         : in IcacheToFetch2Type;
-		i_out        : out Fetch2ToIcacheType;
+	i_in         : in IcacheToFetch2Type;
+	i_out        : out Fetch2ToIcacheType;
 
-		f_in         : in Fetch1ToFetch2Type;
+	f_in         : in Fetch1ToFetch2Type;
 
-		f_out        : out Fetch2ToDecode1Type
+	f_out        : out Fetch2ToDecode1Type
 	);
 end entity fetch2;
 
 architecture behaviour of fetch2 is
-	signal r, rin : Fetch2ToDecode1Type;
+    signal r, rin : Fetch2ToDecode1Type;
 begin
-	regs : process(clk)
-	begin
-		if rising_edge(clk) then
-			-- Output state remains unchanged on stall, unless we are flushing
-			if rst = '1' or flush_in = '1' or stall_in = '0' then
-				r <= rin;
-			end if;
-		end if;
-	end process;
+    regs : process(clk)
+    begin
+	if rising_edge(clk) then
+	    -- Output state remains unchanged on stall, unless we are flushing
+	    if rst = '1' or flush_in = '1' or stall_in = '0' then
+		r <= rin;
+	    end if;
+	end if;
+    end process;
 
-	comb : process(all)
-		variable v : Fetch2ToDecode1Type;
-	begin
-		v := r;
+    comb : process(all)
+	variable v : Fetch2ToDecode1Type;
+    begin
+	v := r;
 
-		-- asynchronous icache lookup
-		i_out.req <= '1';
-		i_out.addr <= f_in.nia;
-		v.valid := i_in.ack;
-		v.nia := f_in.nia;
-		v.insn := i_in.insn;
-		stall_out <= stop_in or not i_in.ack;
+	-- asynchronous icache lookup
+	i_out.req <= '1';
+	i_out.addr <= f_in.nia;
+	v.valid := i_in.ack;
+	v.nia := f_in.nia;
+	v.insn := i_in.insn;
+	stall_out <= stop_in or not i_in.ack;
 
-		if flush_in = '1' or stop_in = '1' then
-			v.valid := '0';
-		end if;
-		v.stop_mark := stop_in;
+	if flush_in = '1' or stop_in = '1' then
+	    v.valid := '0';
+	end if;
+	v.stop_mark := stop_in;
 
-		-- Update registers
-		rin <= v;
+	-- Update registers
+	rin <= v;
 
-		-- Update outputs
-		f_out <= r;
-	end process;
+	-- Update outputs
+	f_out <= r;
+    end process;
 end architecture behaviour;

fpga/toplevel.vhdl

@@ -21,7 +21,7 @@ architecture behaviour of toplevel is
 
     -- Reset signals:
     signal soc_rst : std_ulogic;
-    signal pll_rst_n : std_ulogic;
+    signal pll_rst : std_ulogic;
 
     -- Internal clock signals:
     signal system_clk : std_ulogic;
@@ -38,14 +38,14 @@ begin
 	    pll_clk => system_clk,
 	    pll_locked_in => system_clk_locked,
 	    ext_rst_in => ext_rst,
-	    pll_rst_out => pll_rst_n,
+	    pll_rst_out => pll_rst,
 	    rst_out => soc_rst
 	    );
 
     clkgen: entity work.clock_generator
 	port map(
 	    ext_clk => ext_clk,
-	    pll_rst_in => pll_rst_n,
+	    pll_rst_in => pll_rst,
 	    pll_clk_out => system_clk,
 	    pll_locked_out => system_clk_locked
 	    );

microwatt.core

@@ -26,7 +26,6 @@ filesets:
       - divider.vhdl
       - writeback.vhdl
       - insn_helpers.vhdl
-      - wishbone_debug_master.vhdl
       - core.vhdl
       - icache.vhdl
       - core_debug.vhdl
@@ -68,14 +67,9 @@ filesets:
       - fpga/nexys-video.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 
-  arty_a7-35:
+  arty_a7:
     files:
-      - fpga/arty_a7-35.xdc : {file_type : xdc}
-      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
-
-  arty_a7-100:
-    files:
-      - fpga/arty_a7-35.xdc : {file_type : xdc}
+      - fpga/arty_a7.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 
   cmod_a7-35:
@@ -102,7 +96,7 @@ targets:
 
   arty_a7-35:
     default_tool: vivado
-    filesets: [core, arty_a7-35, soc, fpga, debug_xilinx]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a35ticsg324-1L}
@@ -110,7 +104,7 @@ targets:
 
   arty_a7-100:
     default_tool: vivado
-    filesets: [core, arty_a7-100, soc, fpga, debug_xilinx]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx]
     parameters : [memory_size, ram_init_file]
     tools:
       vivado: {part : xc7a100ticsg324-1L}