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Added support for building for Arty A7 boards

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riktw
2019-08-27 22:20:02 +02:00
parent 95b9f19882
commit 4ebd6fc1f7
2 changed files with 21 additions and 0 deletions
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7
fpga/arty_a7-35.xdc Normal file
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set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }];
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk }];
set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { reset_n }]; #mapped to SW0
set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];