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Merge pull request #96 from antonblanchard/clk_gen_bypass-fix

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Fix clk_gen_bypass
This commit is contained in:
Anton Blanchard
2019-10-13 15:36:37 +11:00
committed by GitHub
parent 8530500a71 6cdb8ca9f5
commit 56908edea2
1 changed files with 8 additions and 3 deletions
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11
fpga/clk_gen_bypass.vhd
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@@ -2,6 +2,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity clock_generator is
generic (
CLK_INPUT_HZ : positive := 50000000;
CLK_OUTPUT_HZ : positive := 50000000
);
port (
ext_clk : in std_logic;
pll_rst_in : in std_logic;
@@ -13,8 +18,8 @@ end entity clock_generator;
architecture bypass of clock_generator is
begin
assert CLK_INPUT_HZ = CLK_OUTPUT_HZ severity FAILURE;
pll_locked_out <= not pll_rst_in;
pll_clk_out <= ext_clk;
pll_locked_out <= not pll_rst_in;
pll_clk_out <= ext_clk;
end architecture bypass;