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execute1: Implement CIABR
CIABR (Completed Instruction Address Breakpoint Register) is an SPR that contains an instruction address. When the instruction at that address completes, the CPU takes a Trace interrupt before executing the next instruction (provided the instruction doesn't cause some other interrupt and isn't an rfid, hrfid or rfscv instruction). Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
parent
f4ec0c2043
commit
5a28f76b6f
@ -64,6 +64,7 @@ package common is
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constant SPR_DSCR : spr_num_t := 17;
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constant SPR_VRSAVE : spr_num_t := 256;
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constant SPR_PIR : spr_num_t := 1023;
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constant SPR_CIABR : spr_num_t := 187;
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-- PMU registers
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constant SPR_UPMC1 : spr_num_t := 771;
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@ -174,6 +175,7 @@ package common is
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constant SPRSEL_CTRL : spr_selector := 4x"a";
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constant SPRSEL_DSCR : spr_selector := 4x"b";
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constant SPRSEL_PIR : spr_selector := 4x"c";
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constant SPRSEL_CIABR : spr_selector := 4x"d";
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constant SPRSEL_XER : spr_selector := 4x"f";
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-- FSCR and HFSCR bit numbers
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@ -275,6 +277,7 @@ package common is
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hfscr_fp: std_ulogic;
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heir: std_ulogic_vector(63 downto 0);
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dscr: std_ulogic_vector(24 downto 0);
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ciabr: std_ulogic_vector(63 downto 0);
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end record;
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constant ctrl_t_init : ctrl_t :=
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(wait_state => '0', run => '1', xer_low => 18x"0",
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@ -488,6 +488,8 @@ architecture behaviour of decode1 is
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i.sel := SPRSEL_DSCR;
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when SPR_PIR =>
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i.sel := SPRSEL_PIR;
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when SPR_CIABR =>
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i.sel := SPRSEL_CIABR;
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when others =>
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i.valid := '0';
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end case;
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@ -96,6 +96,7 @@ architecture behaviour of execute1 is
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set_heir : std_ulogic;
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write_ctrl : std_ulogic;
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write_dscr : std_ulogic;
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write_ciabr : std_ulogic;
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enter_wait : std_ulogic;
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scv_trap : std_ulogic;
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end record;
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@ -116,6 +117,7 @@ architecture behaviour of execute1 is
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start_div : std_ulogic;
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start_bsort : std_ulogic;
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do_trace : std_ulogic;
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ciabr_trace : std_ulogic;
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fp_intr : std_ulogic;
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res2_sel : std_ulogic_vector(1 downto 0);
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bypass_valid : std_ulogic;
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@ -133,6 +135,7 @@ architecture behaviour of execute1 is
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busy: std_ulogic;
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fp_exception_next : std_ulogic;
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trace_next : std_ulogic;
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trace_ciabr : std_ulogic;
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prev_op : insn_type_t;
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prev_prefixed : std_ulogic;
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oe : std_ulogic;
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@ -165,8 +168,8 @@ architecture behaviour of execute1 is
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constant reg_stage1_type_init : reg_stage1_type :=
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(e => Execute1ToWritebackInit, se => side_effect_init,
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busy => '0',
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fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL,
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prev_prefixed => '0',
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fp_exception_next => '0', trace_next => '0', trace_ciabr => '0',
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prev_op => OP_ILLEGAL, prev_prefixed => '0',
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oe => '0', mul_select => "000", res2_sel => "00",
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spr_select => spr_id_init, pmu_spr_num => 5x"0",
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redir_to_next => '0', advance_nia => '0', lr_from_next => '0',
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@ -1157,6 +1160,13 @@ begin
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end if;
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v.do_trace := ex1.msr(MSR_SE);
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-- see if we have a CIABR map
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if ctrl.ciabr(0) = '1' and ctrl.ciabr(1) = not ex1.msr(MSR_PR) and
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ctrl.ciabr(63 downto 2) = e_in.nia(63 downto 2) then
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v.do_trace := '1';
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v.ciabr_trace := '1';
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end if;
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case_0: case e_in.insn_type is
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when OP_ILLEGAL =>
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illegal := '1';
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@ -1392,6 +1402,8 @@ begin
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v.se.write_ctrl := '1';
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when SPRSEL_DSCR =>
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v.se.write_dscr := '1';
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when SPRSEL_CIABR =>
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v.se.write_ciabr := '1';
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when others =>
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end case;
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end if;
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@ -1655,12 +1667,14 @@ begin
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v.e.srr1 := (others => '0');
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v.e.srr1(47 - 33) := '1';
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v.e.srr1(47 - 34) := ex1.prev_prefixed;
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if ex1.prev_op = OP_LOAD or ex1.prev_op = OP_ICBI or ex1.prev_op = OP_ICBT or
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ex1.prev_op = OP_DCBF then
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if (ex1.prev_op = OP_LOAD or ex1.prev_op = OP_ICBI or ex1.prev_op = OP_ICBT or
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ex1.prev_op = OP_DCBF) and ex1.trace_ciabr = '0' then
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v.e.srr1(47 - 35) := '1';
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elsif ex1.prev_op = OP_STORE or ex1.prev_op = OP_DCBZ then
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elsif (ex1.prev_op = OP_STORE or ex1.prev_op = OP_DCBZ) and
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ex1.trace_ciabr = '0' then
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v.e.srr1(47 - 36) := '1';
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end if;
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v.e.srr1(47 - 43) := ex1.trace_ciabr;
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elsif irq_valid = '1' then
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-- Don't deliver the interrupt until we have a valid instruction
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@ -1694,6 +1708,7 @@ begin
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bypass_valid := actions.bypass_valid;
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v.taken_branch_event := actions.take_branch;
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v.trace_next := actions.do_trace;
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v.trace_ciabr := actions.ciabr_trace;
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v.fp_exception_next := actions.fp_intr;
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v.res2_sel := actions.res2_sel;
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v.msr := actions.new_msr;
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@ -1877,6 +1892,7 @@ begin
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assemble_ctrl(ctrl, ex1.msr(MSR_PR)) when SPRSEL_CTRL,
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39x"0" & ctrl.dscr when SPRSEL_DSCR,
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56x"0" & std_ulogic_vector(to_unsigned(CPU_INDEX, 8)) when SPRSEL_PIR,
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ctrl.ciabr when SPRSEL_CIABR,
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assemble_xer(ex1.e.xerc, ctrl.xer_low) when others;
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stage2_stall <= l_in.l2stall or fp_in.f2stall;
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@ -2057,6 +2073,9 @@ begin
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if ex1.se.write_dscr = '1' then
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ctrl_tmp.dscr <= ex1.e.write_data(24 downto 0);
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end if;
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if ex1.se.write_ciabr = '1' then
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ctrl_tmp.ciabr <= ex1.e.write_data;
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end if;
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if ex1.se.enter_wait = '1' then
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ctrl_tmp.wait_state <= '1';
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end if;
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