mirror of
https://github.com/antonblanchard/microwatt.git
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Add PLL for ECP5 device
Means we can synthesize at 40Mhz (where we currently make timing) and our UART still works at 115200 baud. Tested working hello world unmodified with ECP5 eval board. Orange Crab is updated but is untested. Signed-off-by: Michael Neuling <mikey@neuling.org>
This commit is contained in:
Michael Neuling
10
Makefile
10
Makefile
@@ -149,10 +149,10 @@ FPGA_TARGET ?= ORANGE-CRAB
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ifeq ($(FPGA_TARGET), ORANGE-CRAB)
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RESET_LOW=true
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CLK_INPUT=50000000
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CLK_FREQUENCY=50000000
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CLK_FREQUENCY=40000000
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LPF=constraints/orange-crab.lpf
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PACKAGE=CSFBGA285
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NEXTPNR_FLAGS=--um5g-85k --freq 50
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NEXTPNR_FLAGS=--um5g-85k --freq 40
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OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
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OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
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endif
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@@ -161,10 +161,10 @@ endif
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ifeq ($(FPGA_TARGET), ECP5-EVN)
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RESET_LOW=true
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CLK_INPUT=12000000
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CLK_FREQUENCY=12000000
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CLK_FREQUENCY=40000000
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LPF=constraints/ecp5-evn.lpf
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PACKAGE=CABGA381
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NEXTPNR_FLAGS=--um5g-85k --freq 12
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NEXTPNR_FLAGS=--um5g-85k --freq 40
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OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
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OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
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endif
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@@ -172,7 +172,7 @@ endif
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GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
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-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY)
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clkgen=fpga/clk_gen_bypass.vhd
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clkgen=fpga/clk_gen_ecp5.vhd
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toplevel=fpga/top-generic.vhdl
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dmi_dtm=dmi_dtm_dummy.vhdl
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127
fpga/clk_gen_ecp5.vhd
Normal file
127
fpga/clk_gen_ecp5.vhd
Normal file
@@ -0,0 +1,127 @@
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library ieee;
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use ieee.std_logic_1164.all;
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entity clock_generator is
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generic (
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CLK_INPUT_HZ : positive := 12000000;
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CLK_OUTPUT_HZ : positive := 50000000
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);
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port (
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ext_clk : in std_logic;
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pll_rst_in : in std_logic;
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pll_clk_out : out std_logic;
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pll_locked_out : out std_logic
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);
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end entity clock_generator;
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architecture bypass of clock_generator is
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-- prototype of ECP5 PLL
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component EHXPLLL is
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generic (
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CLKI_DIV : integer := 1;
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CLKFB_DIV : integer := 1;
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CLKOP_DIV : integer := 8;
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CLKOS_DIV : integer := 8;
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CLKOS2_DIV : integer := 8;
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CLKOS3_DIV : integer := 8;
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CLKOP_ENABLE : string := "ENABLED";
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CLKOS_ENABLE : string := "DISABLED";
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CLKOS2_ENABLE : string := "DISABLED";
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CLKOS3_ENABLE : string := "DISABLED";
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CLKOP_CPHASE : integer := 0;
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CLKOS_CPHASE : integer := 0;
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CLKOS2_CPHASE : integer := 0;
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CLKOS3_CPHASE : integer := 0;
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CLKOP_FPHASE : integer := 0;
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CLKOS_FPHASE : integer := 0;
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CLKOS2_FPHASE : integer := 0;
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CLKOS3_FPHASE : integer := 0;
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FEEDBK_PATH : string := "CLKOP";
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CLKOP_TRIM_POL : string := "RISING";
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CLKOP_TRIM_DELAY : integer := 0;
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CLKOS_TRIM_POL : string := "RISING";
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CLKOS_TRIM_DELAY : integer := 0;
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OUTDIVIDER_MUXA : string := "DIVA";
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OUTDIVIDER_MUXB : string := "DIVB";
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OUTDIVIDER_MUXC : string := "DIVC";
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OUTDIVIDER_MUXD : string := "DIVD";
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PLL_LOCK_MODE : integer := 0;
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PLL_LOCK_DELAY : integer := 200;
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STDBY_ENABLE : string := "DISABLED";
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REFIN_RESET : string := "DISABLED";
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SYNC_ENABLE : string := "DISABLED";
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INT_LOCK_STICKY : string := "ENABLED";
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DPHASE_SOURCE : string := "DISABLED";
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PLLRST_ENA : string := "DISABLED";
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INTFB_WAKE : string := "DISABLED" );
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port (
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CLKI : in std_logic;
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CLKFB : in std_logic;
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PHASESEL1 : in std_logic;
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PHASESEL0 : in std_logic;
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PHASEDIR : in std_logic;
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PHASESTEP : in std_logic;
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PHASELOADREG : in std_logic;
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STDBY : in std_logic;
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PLLWAKESYNC : in std_logic;
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RST : in std_logic;
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ENCLKOP : in std_logic;
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ENCLKOS : in std_logic;
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ENCLKOS2 : in std_logic;
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ENCLKOS3 : in std_logic;
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CLKOP : out std_logic;
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CLKOS : out std_logic;
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CLKOS2 : out std_logic;
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CLKOS3 : out std_logic;
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LOCK : out std_logic;
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INTLOCK : out std_logic;
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REFCLK : out std_logic;
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CLKINTFB : out std_logic );
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end component;
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signal clkop : std_logic;
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signal lock : std_logic;
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-- PLL constants based on prjtrellis example
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constant PLL_IN : natural := 2000000;
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constant PLL_OUT : natural := 600000000;
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-- Configration for ECP5 PLL
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constant PLL_CLKOP_DIV : natural := PLL_OUT/CLK_OUTPUT_HZ;
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constant PLL_CLKFB_DIV : natural := CLK_OUTPUT_HZ/PLL_IN;
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constant PLL_CLKI_DIV : natural := CLK_INPUT_HZ/PLL_IN;
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begin
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pll_clk_out <= clkop;
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pll_locked_out <= not lock; -- FIXME: EHXPLLL lock signal active low?!?
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clkgen: EHXPLLL
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generic map(
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CLKOP_CPHASE => 11, -- FIXME: Copied from prjtrells.
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CLKOP_DIV => PLL_CLKOP_DIV,
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CLKFB_DIV => PLL_CLKFB_DIV,
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CLKI_DIV => PLL_CLKI_DIV
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)
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port map (
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CLKI => ext_clk,
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CLKOP => clkop,
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CLKFB => clkop,
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LOCK => lock,
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RST => pll_rst_in,
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PHASESEL1 => '0',
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PHASESEL0 => '0',
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PHASEDIR => '0',
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PHASESTEP => '0',
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PHASELOADREG => '0',
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STDBY => '0',
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PLLWAKESYNC => '0',
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ENCLKOP => '0',
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ENCLKOS => '0',
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ENCLKOS2 => '0',
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ENCLKOS3 => '0'
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);
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end architecture bypass;
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