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loadstore1: Fix setting of SRR0 on alignment interrupt

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When an alignment interrupt was being generated, loadstore1 was
setting the l_out.valid signal in one cycle and l_out.interrupt in the
next, for the same instruction.  This meant that the offending
instruction completed and the interrupt was applied to the next
instruction, meaning that SRR0 ended up pointing to the following
instruction.  To fix this, when an access causing an alignment
interrupt is going into r2, we set r2.busy for one cycle and set
r2.one_cycle to 0 so that the complete signal doesn't get asserted.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
2025-01-16 18:57:33 +11:00
parent f64ab6569d
commit 622f8c81cc
1 changed files with 7 additions and 2 deletions
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9
loadstore1.vhdl
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@@ -702,8 +702,13 @@ begin
v.wait_dc := r1.req.valid and r1.req.dc_req and not r1.req.load_sp and
not r1.req.incomplete;
v.wait_mmu := r1.req.valid and r1.req.mmu_op;
v.busy := r1.req.valid and r1.req.mmu_op;
v.one_cycle := r1.req.valid and not (r1.req.dc_req or r1.req.mmu_op);
if r1.req.valid = '1' and r1.req.align_intr = '1' then
v.busy := '1';
v.one_cycle := '0';
else
v.busy := r1.req.valid and r1.req.mmu_op;
v.one_cycle := r1.req.valid and not (r1.req.dc_req or r1.req.mmu_op);
end if;
if r1.req.do_update = '1' or r1.req.store = '1' or r1.req.read_spr = '1' then
v.wr_sel := "00";
elsif r1.req.load_sp = '1' then