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Merge pull request #106 from paulusmack/master

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wishbone_debug_master: Improve timing
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Anton Blanchard 2019-10-15 21:05:10 +11:00 committed by GitHub
commit 640af89e72
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1 changed files with 2 additions and 3 deletions
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wishbone_debug_master.vhdl
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@ -90,9 +90,8 @@ begin
elsif dmi_addr = DBG_WB_CTRL then
reg_ctrl <= dmi_din(10 downto 0);
end if;
end if;
-- Address register auto-increment
if state = WB_CYCLE and (wb_in.ack and reg_ctrl(8))= '1' then
elsif state = WB_CYCLE and (wb_in.ack and reg_ctrl(8))= '1' then
-- Address register auto-increment
reg_addr <= std_ulogic_vector(unsigned(reg_addr) +
decode_autoinc(reg_ctrl(10 downto 9)));
end if;