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Merge pull request #48 from antonblanchard/clk_gen_bypass

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Fix clk_gen_bypass
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Anton Blanchard
2019-09-12 13:03:33 +10:00
committed by GitHub
parent 80aa781454 d89a9929fd
commit 67446709ca
1 changed files with 1 additions and 1 deletions
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fpga/clk_gen_bypass.vhd
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@@ -14,7 +14,7 @@ architecture bypass of clock_generator is
begin
pll_locked_out <= pll_rst_in;
pll_locked_out <= not pll_rst_in;
pll_clk_out <= ext_clk;
end architecture bypass;