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Merge pull request #317 from antonblanchard/gpio-fix

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gpio: Add HAS_GPIO to avoid verilator build errors
This commit is contained in:
Paul Mackerras
2021-08-14 10:18:12 +10:00
committed by GitHub
parent 2bd00f5119 591e96d1a2
commit 71af8016da
2 changed files with 20 additions and 15 deletions
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2
fpga/top-arty.vhdl
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@@ -28,6 +28,7 @@ entity toplevel is
UART_IS_16550 : boolean := false;
HAS_UART1 : boolean := true;
USE_LITESDCARD : boolean := false;
HAS_GPIO : boolean := true;
NGPIO : natural := 32
);
port(
@@ -207,6 +208,7 @@ begin
UART0_IS_16550 => UART_IS_16550,
HAS_UART1 => HAS_UART1,
HAS_SD_CARD => USE_LITESDCARD,
HAS_GPIO => HAS_GPIO,
NGPIO => NGPIO
)
port map (

33
soc.vhdl
View File

@@ -81,7 +81,8 @@ entity soc is
DCACHE_TLB_SET_SIZE : natural := 64;
DCACHE_TLB_NUM_WAYS : natural := 2;
HAS_SD_CARD : boolean := false;
NGPIO : natural := 0
HAS_GPIO : boolean := false;
NGPIO : natural := 32
);
port(
rst : in std_ulogic;
@@ -913,20 +914,22 @@ begin
icp_out => ics_to_icp
);
gpio : entity work.gpio
generic map(
NGPIO => NGPIO
)
port map(
clk => system_clk,
rst => rst_gpio,
wb_in => wb_gpio_in,
wb_out => wb_gpio_out,
gpio_in => gpio_in,
gpio_out => gpio_out,
gpio_dir => gpio_dir,
intr => gpio_intr
);
gpio0_gen: if HAS_GPIO generate
gpio : entity work.gpio
generic map(
NGPIO => NGPIO
)
port map(
clk => system_clk,
rst => rst_gpio,
wb_in => wb_gpio_in,
wb_out => wb_gpio_out,
gpio_in => gpio_in,
gpio_out => gpio_out,
gpio_dir => gpio_dir,
intr => gpio_intr
);
end generate;
-- Assign external interrupts
interrupts: process(all)