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Remove core_files from soc_files and fpga_files
We were already including the core_files at the same time as the soc_files in many targets. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
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committed by
Anton Blanchard
parent
ef01fa32bd
commit
75da4156fe
8
Makefile
8
Makefile
@@ -50,13 +50,13 @@ core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
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loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
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core.vhdl fpu.vhdl
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soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
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soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
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wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
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spi_rxtx.vhdl spi_flash_ctrl.vhdl
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uart_files = $(wildcard uart16550/*.v)
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soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
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soc_sim_files = $(core_files) $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
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sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
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sim_16550_uart.vhdl \
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random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl
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@@ -126,7 +126,7 @@ SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -fa
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sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
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$(CC) $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
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soc_dram_files = $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
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soc_dram_files = $(core_files) $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
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soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
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soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
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dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
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@@ -184,7 +184,7 @@ CLK_FREQUENCY=50000000
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clkgen=fpga/clk_gen_bypass.vhd
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endif
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fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
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fpga_files = fpga/soc_reset.vhdl \
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fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
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nonrandom.vhdl
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