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Remove -add from xdc files

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2021-08-09 13:26:32 +10:00
committed by Anton Blanchard
parent 187199c489
commit 75e06a1e30
4 changed files with 4 additions and 4 deletions
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2
fpga/arty_a7.xdc
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@@ -531,7 +531,7 @@ set_property CONFIG_MODE SPIx4 [current_design]
# Clock constraints
################################################################################
create_clock -add -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
create_clock -name eth_rx_clk -period 40.0 [get_ports { eth_clocks_rx }]

2
fpga/cmod_a7-35.xdc
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@@ -1,6 +1,6 @@
## Clock signal 12 MHz
set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
create_clock -add -name sys_clk_pin -period 83.33 [get_ports {ext_clk}];
create_clock -name sys_clk_pin -period 83.33 [get_ports {ext_clk}];
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];

2
fpga/nexys-video.xdc
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@@ -313,7 +313,7 @@ set_property CONFIG_MODE SPIx4 [current_design]
# Clock constraints
################################################################################
create_clock -add -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
################################################################################
# False path constraints (from LiteX as they relate to LiteDRAM)

2
fpga/nexys_a7.xdc
View File

@@ -1,5 +1,5 @@
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports ext_clk]
create_clock -period 10.000 -name sys_clk_pin -add [get_ports ext_clk]
create_clock -period 10.000 -name sys_clk_pin [get_ports ext_clk]
set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports ext_rst]