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Fix PLL reset signal name in toplevel

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It shouldn't have a _n suffix, it's active positive.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2019-09-11 12:18:22 +01:00
parent 8af2b004c3
commit 79b0b9a046
1 changed files with 3 additions and 3 deletions
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6
fpga/toplevel.vhdl
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@ -21,7 +21,7 @@ architecture behaviour of toplevel is
-- Reset signals:
signal soc_rst : std_ulogic;
signal pll_rst_n : std_ulogic;
signal pll_rst : std_ulogic;
-- Internal clock signals:
signal system_clk : std_ulogic;
@ -38,14 +38,14 @@ begin
pll_clk => system_clk,
pll_locked_in => system_clk_locked,
ext_rst_in => ext_rst,
pll_rst_out => pll_rst_n,
pll_rst_out => pll_rst,
rst_out => soc_rst
);
clkgen: entity work.clock_generator
port map(
ext_clk => ext_clk,
pll_rst_in => pll_rst_n,
pll_rst_in => pll_rst,
pll_clk_out => system_clk,
pll_locked_out => system_clk_locked
);