github.com/antonblanchard.microwatt
1
0
Fork 0
mirror of https://github.com/antonblanchard/microwatt.git synced 2026-02-27 00:59:41 +00:00
Code Releases Activity

Fix a few reset issues in flash controller

Browse Source 
Our flash controller fails when simulating with iverilog. Looking
closer, both wb_stash and auto_last_addr are X state, and things
fall apart after they get used.

Initialise them both fixes the iverilog issue.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2020-12-12 13:19:52 +11:00
committed by Anton Blanchard
parent 081dc64d39
commit 7c8bc85e44
1 changed files with 14 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
spi_flash_ctrl.vhdl
View File

@@ -232,6 +232,10 @@ begin
if rst = '1' then
wb_out.ack <= '0';
wb_out.stall <= '0';
wb_stash.cyc <= '0';
wb_stash.stb <= '0';
wb_stash.sel <= (others => '0');
wb_stash.we <= '0';
else
-- Latch wb responses as well for 1 cycle. Stall is updated
-- below
@@ -344,12 +348,16 @@ begin
auto_sync: process(clk)
begin
if rising_edge(clk) then
auto_state <= auto_next;
auto_cnt <= auto_cnt_next;
auto_data <= auto_data_next;
if auto_latch_adr = '1' then
auto_last_addr <= auto_lad_next;
end if;
if rst = '1' then
auto_last_addr <= (others => '0');
else
auto_state <= auto_next;
auto_cnt <= auto_cnt_next;
auto_data <= auto_data_next;
if auto_latch_adr = '1' then
auto_last_addr <= auto_lad_next;
end if;
end if;
end if;
end process;