Add RAM_512x64

Makefile

@@ -190,10 +190,11 @@ CLK_INPUT=50000000
 CLK_FREQUENCY=50000000
 clkgen=fpga/clk_gen_bypass.vhd
 toplevel=fpga/top-caravel.vhdl
+MEMORY_SIZE=4096
 endif
 
 fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
-	fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
+	fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram_caravel.vhdl \
 	nonrandom.vhdl
 
 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
@@ -206,7 +207,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 
 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c verilator/jtag-verilator.c
-	verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c verilator/jtag-verilator.c -o $@ -Iuart16550 -Ijtag_tap -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
+	verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c verilator/jtag-verilator.c -o $@ -Iuart16550 -Ijtag_tap -Icaravel_bram -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
 	make -C obj_dir -f Vmicrowatt.mk
 	@cp -f obj_dir/microwatt-verilator microwatt-verilator
 

caravel_bram/RAM_512x64.v

@@ -0,0 +1,28 @@
+module RAM_512x64 (
+    input           CLK,
+    input   [7:0]   WE,
+    input           EN,
+    input   [63:0]  Di,
+    output  [63:0]  Do,
+    input   [8:0]   A
+);
+   
+    DFFRAM #(.COLS(2), .filename("even.hex")) LBANK (
+                .CLK(CLK),
+                .WE(WE[3:0]),
+                .EN(EN),
+                .Di(Di[31:0]),
+                .Do(Do[31:0]),
+                .A(A[8:0])
+            );
+
+    DFFRAM #(.COLS(2), .filename("odd.hex")) HBANK (
+                .CLK(CLK),
+                .WE(WE[7:4]),
+                .EN(EN),
+                .Di(Di[63:32]),
+                .Do(Do[63:32]),
+                .A(A[8:0])
+            );
+
+endmodule        

fpga/main_bram_caravel.vhdl

@@ -0,0 +1,63 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+
+entity main_bram is
+    generic(
+        WIDTH        : natural := 64;
+        HEIGHT_BITS  : natural := 11;
+        MEMORY_SIZE  : natural := (8*1024);
+        RAM_INIT_FILE : string
+        );
+    port(
+        clk  : in std_logic;
+        addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ;
+        di   : in std_logic_vector(WIDTH-1 downto 0);
+        do   : out std_logic_vector(WIDTH-1 downto 0);
+        sel  : in std_logic_vector((WIDTH/8)-1 downto 0);
+        re   : in std_ulogic;
+        we   : in std_ulogic
+        );
+end entity main_bram;
+
+architecture behaviour of main_bram is
+    component RAM_512x64 port (
+        CLK : in std_ulogic;
+        WE  : in std_ulogic_vector(7 downto 0);
+        EN  : in std_ulogic;
+        Di  : in std_ulogic_vector(63 downto 0);
+        Do  : out std_ulogic_vector(63 downto 0);
+        A   : in std_ulogic_vector(8 downto 0)
+    );
+    end component;
+
+    signal sel_qual: std_ulogic_vector((WIDTH/8)-1 downto 0);
+
+    signal obuf : std_logic_vector(WIDTH-1 downto 0);
+begin
+    assert WIDTH = 64;
+    -- Do we have a log2 round up issue here?
+    assert HEIGHT_BITS = 10;
+    assert MEMORY_SIZE = (4*1024);
+
+    sel_qual <= sel when we = '1' else (others => '0');
+
+    memory_0 : RAM_512x64
+        port map (
+            CLK  => clk,
+            WE   => sel_qual(7 downto 0),
+            EN   => re or we,
+            Di   => di(63 downto 0),
+            Do   => obuf(63 downto 0),
+            A    => addr(8 downto 0)
+            );
+
+    -- The wishbone BRAM wrapper assumes a 1 cycle delay
+    memory_read_buffer: process(clk)
+    begin
+        if rising_edge(clk) then
+            do <= obuf;
+        end if;
+    end process;
+end architecture behaviour;