Merge pull request #139 from antonblanchard/reduce-mem

Reduce mem

core_tb.vhdl

@@ -19,7 +19,7 @@ begin
     soc0: entity work.soc
 	generic map(
 	    SIM => true,
-	    MEMORY_SIZE => 524288,
+	    MEMORY_SIZE => (384*1024),
 	    RAM_INIT_FILE => "main_ram.bin",
 	    RESET_LOW => false
 	    )

fpga/toplevel.vhdl

@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
 
 entity toplevel is
     generic (
-	MEMORY_SIZE   : positive := 524288;
+	MEMORY_SIZE   : positive := (384*1024);
 	RAM_INIT_FILE : string   := "firmware.hex";
 	RESET_LOW     : boolean  := true;
 	CLK_INPUT     : positive := 100000000;

utils.vhdl

@@ -5,6 +5,7 @@ use ieee.numeric_std.all;
 package utils is
 
     function log2(i : natural) return integer;
+    function log2ceil(i : natural) return integer;
     function ispow2(i : integer) return boolean;
 
 end utils;
@@ -22,6 +23,17 @@ package body utils is
         return ret;
     end function;
 
+    function log2ceil(i : natural) return integer is
+        variable tmp : integer := i;
+        variable ret : integer := 0;
+    begin
+        while tmp >= 1 loop
+            ret  := ret + 1;
+            tmp := tmp / 2;
+        end loop;
+        return ret;
+    end function;
+
     function ispow2(i : integer) return boolean is
     begin
         if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then

wishbone_bram_wrapper.vhdl

@@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
 end entity wishbone_bram_wrapper;
 
 architecture behaviour of wishbone_bram_wrapper is
-    constant ram_addr_bits : integer := log2(MEMORY_SIZE) - 3;
+    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
 
     -- RAM interface
     signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);